MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000000Ah O - Pentium A-step - (TR8) 36-BIT TLB DATA TEST REGISTER
Size:	4 bits
Note:	attempted accesses to this MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. cause an exception on any Pentium except
	  A-step chips, since the 36-bit physical addressing feature was
	  removed from the Pentium prior to general release
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000000Ah


Bitfields for Pentium A-step 36-bit addressing Test Register (TR8):
Bit(s)	Description	(Table R0009)
 63-4	reserved (0)
 3-0	high bits of physical address (A35-A32)
SeeAlso: #R0008