RBIL61 - CACHE CONTROL REGISTER

RBIL61 - CACHE CONTROL REGISTER

INT 1A - PCI BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v2.0c+ - READ CONFIGURATION DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (Intel devices) {#idx36008}{#idx36526}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0119h - PentiumII - "BBL_CR_CTL" - CACHE CONTROL REGISTER {#idx165626}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:011Eh - Pentium II - "BBL_CR_CTL3" L2 CACHE CONTROL REGISTER 3 {#idx165670}

PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips {#idx134684}{#idx134689}{#idx134756}{#idx134772}{#idx136648}{#idx136665}