Interrupt List - Release 61 (16jul00)
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EVENT COUNTER #0
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RBIL61 - EVENT COUNTER #0
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0012h - Pentium, Cyrix 6x86MX - EVENT COUNTER #0
{#idx165213}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
8000h:0012h - Pentium - EVENT COUNTER #0
{#idx166336}