Interrupt List - Release 61 (16jul00)
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INSTRUCTION CACHE END BITS
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RBIL61 - INSTRUCTION CACHE END BITS
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0004h - Pentium -
(TR2)
INSTRUCTION CACHE END BITS
{#idx164847}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
8000h:0004h - Pentium -
(TR2)
INSTRUCTION CACHE END BITS
{#idx166277}