Interrupt List - Release 61 (16jul00)
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PIPELINE
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RBIL61 - PIPELINE
86 Bugs List
{#idx176531}
{#idx176534}
{#idx176537}
INT 1A - PCI
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
v2.0c+ - READ CONFIGURATION
DWORD
Doubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address.
(Intel devices)
{#idx36531}
{#idx36535}
{#idx36613}
{#idx37120}
{#idx38447}
INT 1A - PCI
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
v2.0c+ - READ CONFIGURATION
DWORD
Doubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address.
(OPTi devices)
{#idx33833}
INT 1A - PCI
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
v2.0c+ - READ CONFIGURATION
DWORD
Doubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address.
(VIA Technologies devices)
{#idx34578}
{#idx34605}
{#idx34609}
INT F1 - AQUEDUCT, PIPELINE - GET DATA AREA ADDRESS
{#idx131990}
{#idx131999}
{#idx132002}
{#idx132007}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:000Eh - Pentium, K6, C6 -
(TR12)
NEW FEATURE CONTROL
{#idx165074}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0011h - Pentium, Cyrix 6x86MX - EVENT COUNTER SELECTION AND CONTROL
{#idx165140}
{#idx165163}
{#idx165166}
Opcodes List
{#idx174805}
PORT
IBM PC Portable (uses same BIOS as XT)
0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips
{#idx134694}
{#idx136087}
{#idx136358}
{#idx136362}
{#idx136486}
{#idx136549}
{#idx136552}
{#idx136829}
{#idx137007}
PORT
IBM PC Portable (uses same BIOS as XT)
0024-0027 - PicoPower Vesuvius - V1-LS
{#idx138036}
{#idx138684}
{#idx138706}
PORT
IBM PC Portable (uses same BIOS as XT)
0024-0029 - HEADLAND HTK340 SHASTA 386/486 CHIPSET
{#idx138796}
PORT
IBM PC Portable (uses same BIOS as XT)
00A8-00A9 - Via VT82C496G
"Pluto"
- CONFIGURATION REGISTERS
{#idx141451}
PORT
IBM PC Portable (uses same BIOS as XT)
BEE8-BEE9 - 8514/A and compatible - MULTIFUNCTION CONTROL
{#idx157324}