I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 86h/F1h - ITT VPX 32xx - Output Multiplexor SeeAlso: I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 86h/F0h,I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 86h/F2h Bitfields for VPX 32xx Output Multiplexer: Bit(s) Description (Table I0041) 1-0 port mode 00 parallel output, single clock per pixel 01 double clock port A = FO[23:16] / FO[15:8] on rising/falling PIXCLK port B = FO[7:0] 10 test mode (3220 only) 11 "triple clock" (3220 only) port A = FO[23:16] / FO[15:8] / FO[7:0] port B = FO[7:0] 2 (synchronous mode) data reset during VACT=0 (asynchronous mode) clock slope (=0 positive edge triggered, =1 negative edge triggered) 3 clock source 0 external, PIXCLK is clock source (input) 1 internal, PIXCLK is an output signal 5-4 (synchronous mode) delay signal 00 no delay of "active video" signal with respect to output data 01 one-clock delay 10 two clocks 11 three clocks 6 (3220A, not 3220; async mode) FIFO Empty low-pass filter 7 (3220A, not 3220) enable HLEN (line length counter) SeeAlso: #I0026