MEM A000h:8200h - S3 ViRGE - MEMORY-MAPPED MEMORY-PORT CONTROL REGISTERS        
Size:	40 BYTEs
Note:	the S3 graphics processor registers can be mapped at either
	  linear 000A0000h or at offset 16M from the start of the linear
	  frame buffer


Format of S3 memory-maped port control registers:
Offset	Size	Description	(Table M0070)
8200h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	FIFO control
8204h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	MIU control
8208h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	streams timeout
820Ch	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	miscellaneous timeout
8210h 4 DWORDs	???
8220h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	DMAsee Direct Memory Access read base address
8224h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	DMAsee Direct Memory Access read stride width
SeeAlso: #M0057