MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000000Eh - Pentium, K6, C6 - (TR12) NEW FEATURE CONTROL
Size:	10 bits
Access:	Write
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000000Dh,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000000Eh


Bitfields for Pentium New Feature Control (TR12):
Bit(s)	Description	(Table R0014)
 63-22	reserved (0)
 21	low-power mode enable
 20	(PentiumMMX only) Data CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Inhibit (disable internal data cache)
 19	(PentiumMMX only) Code CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Inhibit (disable internal code cache)
 18-15	reserved (0)
 14	(CPUID=052Bh/052Ch) ignore interrupt immediately after CLI and before
	  STI
 13-10	reserved (0)
 9	enable I/O instruction restart for SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. and use different interrupt
	  priority
 8	generate fast branch-trace message bus cycles
 7	"FTR" ??? (documented as reserved) (0)
 6	disable auto-halt feature (P54C only)
 5	??? (documented as reserved) (0)
 4	disable internal APIC (non-MMX Pentium only)
 3	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Inhibit (disable internal L1 cache)
 2	Single-Pipe Execution (disable V pipeline)
 1	enable special branch trace message cycle on BTB hit (default = 0)
 0	disable branch prediction (no BTB)
Notes:	the AMD K6 only supports bit 3 (cache inhibit) of this register;
	  all other bits should be set to zero
	the Centaur (IDTsee Interrupt Descriptor Table) WinChip C6 supports bits 9, 6, and 3 of this register