MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000033h - Pentium Pro, PentiumII - "TEST_CTL" TEST CONTROL REGISTER
SeeAlso: 32 bits


Bitfields for Pentium Pro MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0033h:
Bit(s)	Description	(Table R0022)
 31	(step sB1 and later) disable LOCK# for locked transactions which
	  are split across a cache line boundary
 30	(step sB1 and later) disable Instruction Streaming buffers
	--used to work around sB1 errata 58 and 59
 29-0	reserved