MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000107h - Centaur (IDTsee Interrupt Descriptor Table) WinChip C6/WinChip2 - Feature Control Register #1 Size: 30 bits SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000108h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000109h Bitfields for Centaur (IDTsee Interrupt Descriptor Table) C6/WinChip2 Feature Control Register #1: Bit(s) Description (Table R0038) 61-31 reserved 30 enable MOV TRx instructions 29 disable CPUID instruction 28 don't use alternative "divide 5 by 2" EFLAGS 0 = use Centaur (IDTsee Interrupt Descriptor Table) flags 1 = use Intel flags 27-26 reserved 25-22 stepping ID 21 reserved 20 enable AMD 3DNow! instructions (WinChip2) 19 enable pairing of MMX instructions (WinChip2) 18-17 reserved 16 enable return stack (default) 15 disable bus pipelining #NA response 14 disable data cache 13 disable instruction cache 12 enable branch predictions (WinChip2+) 11 disable page directory cache 10 reserved 9 enable MMX instructions (default) 8 enable data cache updates for PDE/PTE (C6) 8 disable PDE/PTE update locking (WinChip2) 7 disable check for self-modifying code 6 enable linear burst mode 5 disable #STPCLK support 4 disable machine check exception 3 disable power management 2 enable #MC for internal errors 1 set CPUID feature flag for CMPXCHG8 instruction 0 reserved SeeAlso: #R0039,#R0040