MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 000001D9h - Pentium Pro, PentiumII - "DEBUGCTLMSR" DEBUGGING CONTROL Size: 16 bits Bitfields for Pentium Pro Debugging Control MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.: Bit(s) Description (Table R0049) 63-16 reserved 15 enable execution trace messages 14 enable execution trace messages 13-7 reserved 6 enable execution trace messages 5 performance monitor/BreakpointWhen debugging, a memory location which when accessed causes a break in the normal flow of execution and the invocation of the debugger. Used to let a program run at full speed until a certain instruction is reached or (less frequently) a particular data item is accessed or changed. pins 4 performance monitor/BreakpointWhen debugging, a memory location which when accessed causes a break in the normal flow of execution and the invocation of the debugger. Used to let a program run at full speed until a certain instruction is reached or (less frequently) a particular data item is accessed or changed. pins 3 performance monitor/BreakpointWhen debugging, a memory location which when accessed causes a break in the normal flow of execution and the invocation of the debugger. Used to let a program run at full speed until a certain instruction is reached or (less frequently) a particular data item is accessed or changed. pins 2 performance monitor/BreakpointWhen debugging, a memory location which when accessed causes a break in the normal flow of execution and the invocation of the debugger. Used to let a program run at full speed until a certain instruction is reached or (less frequently) a particular data item is accessed or changed. pins 1 Branch Trap Flag 0 enable Last Branch records (see MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 000001DBh,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 000001DCh)