MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001000h - IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. 386/486 SLC - PROCESSOR OPERATION REGISTER
Size: 19 bits
Access: Read/Write
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001001h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001002h
Bitfields for IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. 386/486 SLC Processor Operation Register:
Bit(s) Description (Table R0053)
63-19 reserved
18 (486SLC only) Low Power PLA
17 (486SLC only) Bus Read
16 (486SLC only) CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Parity Generate Error
15 enable cacheability of NPX operands
14 enable PWI ADS
13 enable Low Power Halt Mode (HLT instruction stops CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock)
12 extended Out instruction (CPU(Central Processing Unit) The microprocessor which executes programs on your computer. waits for READY after any output)
11 cache reload bit
10 enable internal KEN# signal
9 disable cache lock mode
8 reserved
7 enable cache
6 enable DBCS
5 enable Power Interrupt
4 enable FlushTo force the copying of any data still stored in temporary buffers to its final destination. Snooping
3 enable Snoop Input
2 address line A20(Address line 20) The 80286 and higher CPUs allow addresses in real mode to extend slightly beyond the one megabyte mark, which causes an incompatibility with some older programs which expect such addresses to wrap back to the beginning of the address space. For complete compatibility with the 8088, newer machines thus contain circuitry which permits the twenty-first address line (A20) to be disabled. The CPU then effectively has only twenty address lines in real mode, just as the 8088 does, and addresses which would extend beyond the one megabyte mark wrap to the beginning of the address space. See also High Memory Area, Real Mode. mask (see also #02753,#P0415)
1 enable cache parity checking
0 CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Parity Error occurred
SeeAlso: #R0054,#R0055