MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 80000019h - Pentium - FLOATING POINT - LAST PREFETCHED OPCODE
Size:	11 bits
Access:	Read
Desc:	this register stores the opcode of the last floating-point opcode to
	  be prefetched by the CPU(Central Processing Unit) The microprocessor which executes programs on your computer.
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000001Ah,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000001Bh


Bitfields for Pentium Floating-Point Opcode:
Bit(s)	Description	(Table R0057)
 63-11	reserved (0)
 10-8	low three bits of first byte of floating-point instruction
 7-0	second byte of floating-point instruction
Note:	both a standalone FWAIT and the instruction D8h 9Bh are represented
	  as 09Bh