INT 1A - PCI BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v2.0c+ - READ CONFIGURATION DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address. (DEC device)
	AX = B10Ah subfn 1011h
	BH = bus number
	BL = device/function number (bits 7-3 device, bits 2-0 function)
	DI = register number (0000h-00FFh) (see #00878)
Return: CF clear if successful
	    ECX = dword read
	CF set on error
	AH = status (00h,87h) (see #00729)
	EAX, EBX, ECX, and EDX may be modified
	all other flags (except IF) may be modified
Notes:	this function may require up to 1024 byte of stack; it will not enable
	  interrupts if they were disabled before making the call
	the meanings of BL and BH on entry were exchanged between the initial
	  drafts of the specification and final implementation
SeeAlso: AX=B10Ah,AX=B10Ah/SF=8086h


Format of DEC DC21140/DC21040/DC21041 Tulip {Fast/Plus} Ethernet:
Offset	Size	Description	(Table 00923)
 00h 64 BYTEs	header (see #00878)
		(vendor ID 1011h, device ID 0014h)
 10h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	base I/O port for access to control/status registers
 14h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	base memory address for access to control/status registers
 40h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	configuration driver area
		bit 31: sleep mode   \ only one of bits 31,30 may be set
		bit 30: snooze mode  /
		bits 15-8: device driver's use
!!!digital\21041hm.pdf p.34   digital\21140ahm.pdf p.35
SeeAlso: #00742


Format of DEC 21052 PCI-PCI bridge PCI configuration data:
Offset	Size	Description	(Table 00924)
 00h 64 BYTEs	header, type 1 (see #00878)
		(vendor ID 1011h, device ID 0021h)
 40h	BYTE	chip control
 41h	BYTE	diagnostic control
 42h	BYTE	burst counter
 43h	BYTE	SErr disable
 44h	BYTE	primary target wait timer
 45h	BYTE	secondary target wait timer
 46h  2 BYTEs	reserved
 48h	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	count of secondary write attempts
 4Ch	DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.	count of primary write attempts
 50h 44 DWORDs	reserved
!!!digital\21052ds.pdf p.117
SeeAlso: #00742