INT 1A - PCI BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v2.0c+ - READ CONFIGURATION DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (Intel devices) AX = B10Ah subfn 8086h BH = bus number BL = device/function number (bits 7-3 device, bits 2-0 function) DI = register number (0000h-00FFh) (see #00878) Return: CF clear if successful ECX = dword read CF set on error AH = status (00h,87h) (see #00729) EAX, EBX, ECX, and EDX may be modified all other flags (except IF) may be modified Notes: this function may require up to 1024 byte of stack; it will not enable interrupts if they were disabled before making the call the meanings of BL and BH on entry were exchanged between the initial drafts of the specification and final implementation SeeAlso: AX=B10Ah,AX=B10Ah/SF=1106h,AX=B10Dh Format of PCI Configuration data for Intel 82375 EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). Bridge: Offset Size Description (Table 01054) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 0482h) (revision numbers: 03h = 82375EB, 04h = 82375SB) 40h BYTE PCI Control !!!intel\29047704.pdf pg. 32 41h BYTE PCI Arbiter Control 42h BYTE PCI Arbiter Priority Control 43h BYTE PCI Arbiter Priority Control Extension 44h BYTE MEMCS# Control 45h BYTE MEMCS# Bottom of Hole 46h BYTE MEMCS# Top of Hole 47h BYTE MEMCS# Top of Memory 48h WORD EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). Address Decode Control 1 4Ah 2 BYTEs reserved 4Ch BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. I/O Recovery Time Control 4Dh 7 BYTEs reserved 54h BYTE MEMCS# Attribute Register #1 55h BYTE MEMCS# Attribute Register #2 56h BYTE MEMCS# Attribute Register #3 57h BYTE reserved 58h BYTE PCI Decode Control 59h BYTE reserved 5Ah BYTE EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). Address Decode Control 2 5Bh BYTE reserved 5Ch BYTE EISA-to-PCI Memory Region Attributes 5Dh 3 BYTEs reserved 60h 4 DWORDs EISA-to-PCI Memory Region Address registers 1-4 70h 4 DWORDs EISA-to-PCI I/O Region Address registers 1-4 80h WORD BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Timer base address 82h 2 BYTEs reserved 84h BYTE EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). Latency Timer Control Register 85h 3 BYTEs reserved 88h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. PCEB Test Control Register ("DO NOT WRITE") 8Ch 116 BYTEs reserved SeeAlso: #00878,#01055 Format of PCI Configuration data for Intel 82434LX/NX CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through./DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Controller: Offset Size Description (Table 01055) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 04A3h) (revision numbers: 01h/03h are 82434LX, 1xh are 82434NX) (command register only supports bits 8,6,2,1,0) 40h 16 BYTEs unused (hard-wired to 00h) 44h BYTE ??? (AMIAmerican Megatrends, Inc.(American Megatrends, Inc.) A hardware, software and firmware company founded in 1985. BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. writes 00h) 45h BYTE ??? (AMIAmerican Megatrends, Inc.(American Megatrends, Inc.) A hardware, software and firmware company founded in 1985. BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. writes 00h) 50h BYTE Host CPU(Central Processing Unit) The microprocessor which executes programs on your computer. Selection (see #01056) 51h BYTE deturbo frequency control register when deturbo mode is selected (see PORTIBM PC Portable (uses same BIOS as XT) 0CF9h), the chipset places a hold on the memory bus for a fraction of the time inversely proportional to the value in this register by comparing it against a free-running 8-bit counter counting at 1/8 the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock speed (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.) (only bits 7-6 writable, bits 5-0 hardwired to 0) 52h BYTE Secondary CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control (see #01057) 53h BYTE Host Read/Write Buffer Control (see #01058) 54h BYTE PCI Read/Write Buffer Control bits 7-3: reserved bit 2: LBXs connected to TRDY# bit 1: enable PCI burst writes bit 0: enable PCI-to-memory posted writes 55h 2 BYTEs reserved 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control (see #01059) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing (see also #01117) bits 7-2: reserved bit 1: (NX only) RAS# Wait State bit 0: CASsee Communicating Applications Specification# Wait State (one extra wait state before CASsee Communicating Applications Specification# within burst cycle) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 8 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-7 (chip revisions numbered < 10h [LX] only support six rows of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM.) each register N indicates the amount of cumulative amount of memory in SIMM banks 0-N, in multiples of 1M; offset 67h (65h on 82434LX's) contains the total amount of memory installed in the system; on the 82434NX, two additional bits are concatenated to each row boundary from the DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary Extension registers to allow up to 1024M of memory to be specified (though only 512M are supported) 68h 4 BYTEs (NX only) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary Extension registers each nybble is concatenated with the corresponding DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary register to form a 12-bit boundary value (of which only the low 10 bits are actually used) 6Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. reserved (hardwired to 00000000h) 70h BYTE Error Command (see #01060) 71h BYTE Error Status (see #01061) 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. control (see also #01123) bits 7-6: reserved bit 5: map SMM-mode memory (64K) into address space when bits 2-0 = 010 (default 3000h:0000h; can be changed by first SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. event) bit 4: close SMRAM space (allows data accesses to be forwarded to PCI bus while execuding SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. code) bit 3: lock SMRAM space (can't be cleared by software) bits 2-0: SMRAM memory address (010 = Axxxxh, 011 = Bxxxxh) 73h 5 BYTEs reserved 78h WORD Memory Space Gap bit 15: enable ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. hole bits 14-12: size of ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. hole in MB (less 1); must be power of 2 bits 11-8: reserved bits 7-4: bottom of ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. memory hole in MB (must be multiple of gap size) bits 3-0: reserved 7Ah 2 BYTEs reserved 7Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Frame Buffer Range (see #01062) 80h 128 BYTEs reserved Note: the 82434NX is part of the Intel Neptune chipset SeeAlso: #01064,#01083 Bitfields for Intel 82434LX/NX Host CPU(Central Processing Unit) The microprocessor which executes programs on your computer. Selection: Bit(s) Description (Table 01056) 7-5 host CPU(Central Processing Unit) The microprocessor which executes programs on your computer. type LX: hardwired to 100 (Pentium) NX: "reserved" (101 on RB's system) 4-3 reserved 2 enable L1 cache 1-0 Host Operating Frequency (set according to external bus speed) 00: reserved 01: 50 MHz 10: 60 MHz 11: 66 MHz (LX: bit 1 reserved, only 60/66 MHz supported) SeeAlso: #01055,#01057 Bitfields for Intel 82434LX/NX Secondary CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control: Bit(s) Description (Table 01057) 7-6 secondary cache size 00 none 01 reserved 10 256K 11 512K 5 SRAM(Static Random Access Memory) RAM which typically consists of one flip-flop per bit of memory. Unlike DRAMs, static RAM retains its contents as long as power is applied. Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip. See also DRAM. type 0 standard SRAMs 1 burst SRAMs 4 secondary cache allocation 0 cache only CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reads of memory with CACHE# asserted 1 cache all CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reads of cacheable memory 3 CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Byte Control 0 use single write enable and per-byte select lines 1 use per-byte write enables on the cache 2 (NX only) SRAM(Static Random Access Memory) RAM which typically consists of one flip-flop per bit of memory. Unlike DRAMs, static RAM retains its contents as long as power is applied. Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip. See also DRAM. connectivity 0 disable CCS[1:0]# / CCS1# functionality 1 enable CCS[1:0]# functionality to de-select async SRAMs, placing them in a low-power standby mode 1 enable CCS1# functionality for burst SRAMs, indicating the lack of an external address latch 1 (LX only) Secondary CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Write Policy 0 write-through 1 write-back (NX is always in write-back mode) 0 Secondary CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Enable SeeAlso: #01055,#01058 Bitfields for Intel 82434LX/NX Host Read/Write Buffer Control: Bit(s) Description (Table 01058) 7-4 reserved 3 enable read-around-write 2 reserved 1 enable CPU-to-PCI posted writes 0 (LX only) enable CPU-to-memory posted writes (NX always posts memory writes) SeeAlso: #01055,#01057 Bitfields for Intel 82434LX/NX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control: Bit(s) Description (Table 01059) 7-6 (NX only) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. burst timing 00 X-4-4-4 read/write (default) 01 X-4-4-4 read, X-3-3-3 write 10 reserved 11 X-3-3-3 read/write 5 parity error mask 4 0-Active RAS# mode 3 SMRAM enable (must be set to enable reg 72h) 2 Burst-of-Four RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. 1 RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Type =0 RAS#-only =1 CASsee Communicating Applications Specification#-before-RAS# 0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Enable SeeAlso: #01055 Bitfields for Intel 82434LX/NX Error Command register: Bit(s) Description (Table 01060) 7 assert SERR# on receiving target abort 6 assert SERR# on PCI data-write parity error 5 (NX only) assert SERR# on PCI data-read parity error 4 (NX only) assert SERR# on PCI address parity error 3 (NX only) assert PERR# on data parity error 2 enable L2 cache parity 1 enable SERR# on DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM./L2 cache data parity error 0 assert PEN# on data reads; allow CPU(Central Processing Unit) The microprocessor which executes programs on your computer. to signal parity error via PCHK# Notes: PCI command register bit 6 is master enable for bit 3; PCI cmd bits 6 and 8 are the master enable for bits 7-4 and 1 bits 1-0 = 10 is not permitted SeeAlso: #01055,#01061 Bitfields for Intel 82434LX/NX Error Status register: Bit(s) Description (Table 01061) 7 reserved 6 PCI-write detected parity error 5 (NX only) PCI-read detected parity error 4 (NX only) PCI address parity error detected 3 main memory data parity error 2 L2 cache data parity error 1 reserved 0 Shutdown cycle detected Note: clear status bits by writing a 'one' bit to each bit to be cleared SeeAlso: #01060,#01055 Bitfields for Intel 82434LX/NX Frame Buffer Range register: Bit(s) Description (Table 01062) 31-20 buffer offset (in 1MB increments; must be multiple of buffer set set by bits 3-0) 19-14 reserved 13 enable byte merging 12 128K VGA-range Attribute Enable when set, bits 13,9,7 also apply to VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. memory range (Axxxx-Bxxxx) 11-10 reserved 9 no lock requests 8 reserved 7 enable transparent bufer writes 6-4 reserved 3-0 buffer size in MB (less 1); must be power of 2 Note: if bits 31-20=0, the frame buffer feature is disabled SeeAlso: #01055 Format of PCI Configuration data for Intel 82424 CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Controller: Offset Size Description (Table 01063) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 0483h) 40h BYTE bus number 41h BYTE subordinate bus number 42h BYTE disconnect timer 50h BYTE host CPU(Central Processing Unit) The microprocessor which executes programs on your computer. selection 51h BYTE deturbo frequency control when deturbo mode is selected (see PORTIBM PC Portable (uses same BIOS as XT) 0CF9h), the chipset places a hold on the memory bus for a fraction of the time inversely proportional to the value in this register (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.) 52h BYTE secondary cache control 53h BYTE write buffer control 54h BYTE PCI features control 55h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Operation Mode Select 56h BYTE System ExceptionA signal by the CPU that some error condition has been encountered that it can not deal with without a program's intervention. The most commonly encountered exceptions on Intel processors are Exceptions 12 and 13 (decimal, how Intel specifies exception numbers), which are stack and general problems, respectively. Exception 13 is typically caused by a memory access which wraps from the end of a segment back to the beginning. Handling 57h BYTE SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Control Register 58h BYTE reserved 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see also #01118) 60h 4 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-3 each register N indicates amount of memory in rows 0-N (each row is 64 bits wide) boundary register 3 (offset 63h) contains the total system memory, which may not exceed 128M 64h 4 BYTEs unused??? 68h WORD Memory Hole-0 6Ah WORD Memory Hole-1 Note: the above field names are those given by EduWARE's PCI Configuration Manager v1.2 SeeAlso: #01055,#01083,#01108 Format of PCI Configuration data for Intel 82378 and 82379 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Bridges: Offset Size Description (Table 01064) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 0484h) (revision ID: bits 7-4: reserved bits 3-0: revision 0011 82378ZB A0-step 1000 82379AB A0-step) 40h BYTE PCI Control (see #01065) 41h BYTE PCI Arbiter Control (see #01066) 42h BYTE PCI Arbiter Priority Control (see #01067) 43h BYTE (82378ZB) PCI Arbiter Priority Control Extension Register bit 0: bank 3 fixed priority mode select (see also #01067) =0 REQ2# has higher priority =1 REQ3# has higher priority 44h BYTE MEMCS# Control (see #01068) 45h BYTE MEMCS# Bottom of Hole (address bits 23-16) 46h BYTE MEMCS# Top of Hole (address bits 23-16) 47h BYTE MEMCS# Top of Memory (address bits 28-21 == size in 2M increments, less 1) 48h BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Address Decoder Control (see #01069) 49h BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Address Decoder ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. Block Enable (see #01070) 4Ah BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Address Decoder Bottom of Hole (address bits 23-16) 4Bh BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Address Decoder Top of Hole (address bits 23-16) 4Ch BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Controller Recovery Time (see #01087) 4Dh BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Clock Divisor (see #01071) 4Eh BYTE Utility Bus Chip Select Enable A (see #01072) 4Fh BYTE Utility Bus Chip Select Enable B (see #01073) 50h 4 BYTEs reserved 54h BYTE MEMCS# Attribute Register #1 (see #01074) attributes for 16K blocks from C0000h-CFFFFh 55h BYTE MEMCS# Attribute Register #2 (see #01074) attributes for 16K blocks from D0000h-DFFFFh 56h BYTE MEMCS# Attribute Register #3 (see #01074) attributes for 16K blocks from E0000h-EFFFFh 57h BYTE (82378) Scatter/GatherA technique in which the contiguous data of a disk sector or sectors is transferred to or from multiple non-contiguous areas of memory. When reading into multiple areas of memory, this is called a scatter-read; the opposing operation is called gather-write. Relocation Base Adress (see #01075) (82379AB) reserved 58h 8 BYTEs reserved 60h BYTE (82378ZB) IRQ0# Route Control (see #01076) 61h BYTE (82378ZB) IRQ1# Route Control (see #01076) 62h BYTE (82378ZB) IRQ2# Route Control (see #01076) 63h BYTE (82378ZB) IRQ3# Route Control (see #01076) 64h 12 BYTEs reserved 70h BYTE (82378) reserved (82379AB, write-only) PIC/APIC Configuration Control (see #01077) 71h BYTE (82378) reserved (82379AB, write-only) APIC Base Address Relocation (see #01078,MEM FEC00000h) 72h 14 BYTEs reserved 80h WORD BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. timer base address (see PORTIBM PC Portable (uses same BIOS as XT) 0078h) bits 15-2 are bits 15-2 of BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. timer port address bit 1: reserved (0) bit 0: timer enabled (if disabled, other bits ignored) 82h 30 BYTEs unused??? A0h BYTE SMI Control (see #01079) A1h BYTE reserved A2h WORD SMI Enable (see #01080) A4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. System Event Enable (SEE) (see #01081) A8h BYTE Fast-Off Timer (in minutes) A9h BYTE reserved AAh WORD active SMI Requests (see #01082) ACh BYTE (82378ZB) Clock Throttle STPCLK# Low Timer duration of STPCLK# low period in 32 microsecond units ADh BYTE reserved AEh BYTE (82378ZB) Clock Throttle STPCLK# High Timer duration of STPCLK# high period in 32 microsecond units AFh 81 BYTEs reserved SeeAlso: #01055,#01167,PORTIBM PC Portable (uses same BIOS as XT) 040Ah"82378ZB" Bitfields for Intel 82378/82379 PCI Control: Bit(s) Description (Table 01065) 7 reserved (0) 6 DMAsee Direct Memory Access Reserved Page RegisterA peripheral register or I/O port used to extend the addressing range of some other register or I/O port. The prime example are the DMA page registers, which allow the DMA controller to address more than 64K (since the DMA controller only contains 16 address lines; this is the cause of the 64K DMA boundaries). Aliasing Control =0 alias PORTIBM PC Portable (uses same BIOS as XT) 80h-8Fh to PORTIBM PC Portable (uses same BIOS as XT) 90h-9Fh 5 Interrupt Acknowledge Enable =0 ignore INTA cycles on the PCI bus, but still allow 8259 register access and poll-mode functions 4-3 Subtractive Decoding Sample Point 00 slow sample point 01 typical 10 fast sample point 11 reserved 2 PCI Posted Write Buffer Enable 1 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Master Line Buffer Configuration =0 single-transaction mode =1 eight-byte mode for ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. bus master transfers 0 DMAsee Direct Memory Access Line Buffer Configuration =0 single-transaction mode =1 eight-byte mode SeeAlso: #01064,#01066 Bitfields for Intel 82378/82379 PCI Arbiter Control: Bit(s) Description (Table 01066) 7-5 reserveed (0) 4-3 Master Retry Timer 00 disabled (retries never masked) 01 retries unmasked after 16 PCICLKs 10 retries unmasked after 32 PCICLKs 11 retries unmasked after 64 PCICLKs 2 Bus ParkTo move a hard disk's read/write heads to a position in which it is safe to turn off the power and transport the disk drive. Many drives also lock the heads into position when they are parked, providing additional protection from sudden movement. =1 park CPUREQ# on PCI bus when 82378 detects PCI bus idle 1 Bus Lock =0 resource lock =1 Bus lock 0 Guaranteed Access Time =1 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. bus masters are guaranteed 2.5 microsecond CHRDY time-out SeeAlso: #01064,#01065 Bitfields for Intel 82378/82379 PCI Arbiter Priority Control: Bit(s) Description (Table 01067) 7 bank 3 rotate control 6 bank 2 rotate control 5 bank 1 rotate control 4 bank 0 rotate control 3 bank 2 fixed priority mode select B 2 bank 2 fixed priority mode select A 1 bank 1 fixed priority mode select 0 bank 0 fixed priority mode select Note: if both 'rotate' and 'fixed' bits are set for a given bank, that bank will be in rotating-priority mode SeeAlso: #01064,#01066 Bitfields for Intel 82378/82379 MEMCS# Control Register: Bit(s) Description (Table 01068) 7-5 reserved (0) 4 MEMCS# Master Enable 3 write enable for 0F0000h-0FFFFFh 2 read enable for 0F0000h-0FFFFFh 1 write enable for 080000h-09FFFFh 0 read enable for 080000h-09FFFFh SeeAlso: #01064 Bitfields for Intel 82378/82379 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Address Decoder Control Register: Bit(s) Description (Table 01069) 7-4 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. memory cycle forwarding to PCI 0000-1111 = 1M-16M top of ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. memory; any accesses above programmed limit are forwarded to PCI bus 3-0 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA./DMAsee Direct Memory Access memory cycle to PCI bus enables bit 3: 896K-960K (E000h-EFFFh) bit 2: 640K-768K (A000h-BFFFh) bit 1: 512K-640K (8000h-9FFFh) bit 0: 0K-512K (0000h-7FFFh) SeeAlso: #01064,#01070 Bitfields for Intel 82378/82379 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Address Decoder ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. Block Enable: Bit(s) Description (Table 01070) 7 enable 880K-896K (EC00h-EFFFh) 6 enable 864K-880K (E800h-EBFFh) 5 enable 848K-864K (E400h-E7FFh) 4 enable 832K-848K (E000h-E3FFh) 3 enable 816K-832K (DC00h-DFFFh) 2 enabel 800K-816K (D800h-DBFFh) 1 enable 784K-800K (D400h-D7FFh) 0 enable 768K-784K (D000h-D3FFh) Note: ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. accesses within any enabled ranges are forwarded to the PCI bus SeeAlso: #01064,#01069 Bitfields for Intel 82378/82379 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Clock Divisor Register: Bit(s) Description (Table 01071) 7 reserved (0) 6 enable positive decode of upper 64K BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. at 000F0000h-000FFFFFh, FFEF0000h-FFEFFFFFh, and FFFF0000h-FFFFFFFFh 5 coprocessor error enable =1 FERR# is driven onto IRQ13 4 IRQ12/Mouse Function Enable =0 standard IRQ12 =1 mouse 3 RSTDRV enable =1 assert RSTDRV until this bit cleared (for use in changing ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. bus speed) 2-0 PCICLK-to-ISA SYSCLK divisor 000 4 001 3 other reserved SeeAlso: #01064,#01069 Bitfields for Intel 82378/82379 Utility Bus Chip Select A Register: Bit(s) Description (Table 01072) 7 extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. enable (decode accesses to FFF80000h-FFFDFFFFh) 6 lower BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. enable (decode accesses to E0000h-EFFFFh, FFEE0000h-FFEEFFFFh, and FFFE0000h-FFFEFFFFh) 5 (82378ZB) floppy disk primary/secondary address select =1 use secondary address range 4 (82378ZB) IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. Decode enable 3,2 floppy disk address locations enable 1 keyboard controller address location enable enables I/O addresses 60h,62h,64h,66h (82378ZB) or 60h/64h (82379AB) 0 RTCsee Real-Time Clock address location enabled =1 enable decode of I/O ports 70h-77h SeeAlso: #01064,#01089,#01073 Bitfields for Intel 82378ZB/82379 Utility Bus Chip Select B Register: Bit(s) Description (Table 01073) 7 configuration RAM(Random Access Memory) See also DRAM, SRAM. decode enable =1 permit write accesses to I/O port 0C00h and r/w to ports 08xxh 6 enable PORTIBM PC Portable (uses same BIOS as XT) 0092h 5-4 parallel port enable 00 LPT1 (ports 03BCh-03BFh) 01 LPT2 (ports 0378h-037Fh) 10 LPT3 (ports 0278h-027Fh) 11 disabled 3-2 serial port B enable 00 COM1 (03F8h-03FFh) 01 COM2 (02F8h-02FFh) 10 reserved 11 port B disabled 1-0 serial port A enable 00 COM1 (03F8h-03FFh) 01 COM2 (02F8h-02FFh) 10 reserved 11 port A disabled Note: if both serial ports are set to the same address, port B is disabled SeeAlso: #01064,#01072,PORTIBM PC Portable (uses same BIOS as XT) 0092h Bitfields for Intel 82378/82379 MEMCS# Attribute Register 1/2/3: Bit(s) Description (Table 01074) 7 write-enable xC000h-xFFFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 6 read-enable xC000h-xFFFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 5 write-enable x8000h-xBFFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 4 read-enable x8000h-xBFFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 3 write-enable x4000h-x7FFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 2 read-enable x4000h-x7FFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 1 write-enable x0000h-x3FFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. 0 read-enable x0000h-x3FFFh expansion ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. Note: x = C/D/E depending on the attribute register SeeAlso: #01064 Bitfields for Intel 82378ZB Scatter Gather Relocation Base Address: Bit(s) Description (Table 01075) 7-0 bits 15-8 of base address for scatter/gather I/O ports (default 04h; low 8 bits of address are always 10h-3Fh) SeeAlso: #01064,#01074,#01076,PORTIBM PC Portable (uses same BIOS as XT) 040Ah"82378ZB",#P0039 Bitfields for Intel 82371/82378/82379 PCI IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Route Control Register: Bit(s) Description (Table 01076) 7 disable IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. routing 6-4 reserved (0) 3-0 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. number to which to route the PCI IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Note: IRQs 0-2, 8, and 13 are reserved SeeAlso: #01064,#01167,#01100 Bitfields for Intel 82379AB PIC/APIC Configuration Control Register: Bit(s) Description (Table 01077) 7-2 reserved 1 SMI Routing Control =1 SMI via APIC =0 SMI via SMI# signal 0 INT Routing Control =1 INT disabled (requires that APIC be enabled) =0 INT enabled SeeAlso: #01064,#01078 Bitfields for Intel 82379AB/82371 APIC Base Address Relocation: Bit(s) Description (Table 01078) 7 reserved 6 (82379AB) reserved 6 (82371) A12 mask =1 ignore address bit 12 in APIC address 5-0 bits 15-10 of APIC memory address (ORed with FEC00000h to form base address) SeeAlso: #01064,#01167,#01077,MEM FEC00000h Bitfields for Intel 82378/82379 SMI Control Register: Bit(s) Description (Table 01079) 7 reserved 6 (82378) reserved (82379) require Stop Grant bus cycle before asserting STPCLK# 5-4 reserved 3 Fast-Off Timer freeze 2 STPCLK# scaling enable =1 enable Clock Throttle bytes in PCI configuration space 1 STPCLK# signal enable =1 assert STPCLK# on read from PORTIBM PC Portable (uses same BIOS as XT) 00B2h 0 SMI# Gate =1 enable SMI# on system management interrupt Notes: bit 1 is cleared either with an explicit write of 0 here, or by any write to PORTIBM PC Portable (uses same BIOS as XT) 00B2h bit 0 does not affect the recording of SMI events, so a pending SMI will cause an immediate SMI# when the bit is set SeeAlso: #01064,#01080,#01081,#01222,PORTIBM PC Portable (uses same BIOS as XT) 00B2h Bitfields for Intel 82371/82378/82379 SMI Enable Register: Bit(s) Description (Table 01080) 15-9 reserved 8 (82371SB only) Legacy USBsee Universal Serial Bus SMI enable 7 APMC Write SMI enable =1 generate SMI on write to PORTIBM PC Portable (uses same BIOS as XT) 00B2h 6 EXTSMI# SMI enable 5 Fast-Off Timer SMI enable 4 IRQ12 (PS/2IBM PS/2, any model mouse) SMI enable 3 IRQ8 (RTCsee Real-Time Clock alarm) SMI enable 2 IRQ4 (COM1/COM3) SMI enable 1 IRQ3 (COM2/COM4) SMI enable 0 IRQ1 (keyboard) SMI enable SeeAlso: #01064,#01079,#01081,#01167,PORTIBM PC Portable (uses same BIOS as XT) 00B2h Bitfields for Intel 82371/82378/82379 System Event Enable Register: Bit(s) Description (Table 01081) 31 Fast-Off SMI enable (system and break events) 30 (82379 only) Fast-Off Interrupt Enable (break events only) 30 (82371 only) INTR enable (break events only) 29 Fast-Off NMIsee Non-Maskable Interrupt enable (system and break events) 28 (82371SB only) Fast-Off APIC enable (break events only) 27 (82379 only) Fast-Off COM enable (system events only) 26 (82379 only) Fast-Off LPTAbbreviation for Line PrinTer. enable (system events only) 25 (82379 only) Fast-Off Drive enable (system events only) 24 (82379 only) Fast-Off DMAsee Direct Memory Access enable (system events only) 23-16 reserved 15-3 Fast-Off IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. (15-3) enable (system and break events) 2 reserved 1-0 Fast-Off IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. (1-0) enable (system and break events) Note: any enabled system event restarts the Fast-Off Timer, thus preventing a Fast-Off powerdown; any enabled break event awakens the system from powerdown SeeAlso: #01064,#01079,#01080,#01082,#01167 Bitfields for Intel 82371/82378/82379 SMI Request Register: Bit(s) Description (Table 01082) 15-9 reserved 8 (82371SB only) Legacy USBsee Universal Serial Bus SMI status 7 APM SMI Status (write to PORTIBM PC Portable (uses same BIOS as XT) 00B2h triggered SMI) 6 EXTSMI# SMI Status (EXTSMI# line triggered SMI) 5 Fast-Off Timer expired 4 IRQ12 triggered SMI 3 IRQ8 triggered SMI 2 IRQ4 triggered SMI 1 IRQ3 triggered SMI 0 IRQ1 triggered SMI Note: software must explicitly reset the appropriate bits SeeAlso: #01064,#01081,#01167 Format of PCI Configuration data for Intel 82425EX PSC: Offset Size Description (Table 01083) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 0486h) 40h BYTE PCI control register (see #01084) 41h 3 BYTEs ??? 44h BYTE host device control register (see #01085) 45h 3 BYTEs ??? 48h WORD PCI local-bus IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. control register (see #01086) 4Ah 2 BYTEs ??? 4Ch BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. I/O recovery timer register (see #01087) 4Dh BYTE part revision register (see #01088) 4Eh BYTE X-bus Chip Select A register (see #01089) 4Fh BYTE X-bus Chip Select B register??? (see also #01102) 50h BYTE host select register 51h BYTE deturbo frequency control register when deturbo mode is selected (see PORTIBM PC Portable (uses same BIOS as XT) 0CF9h), the chipset places a hold on the memory bus for a fraction of the time inversely proportional to the value in this register (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.) 52h WORD secondary (L2) cache control register 54h 2 BYTEs ??? 56h WORD DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. control register 58h BYTE ??? 59h 7 BYTEs Programmable Attribute Map (PAM) registers 0-6 (see also #01118) 60h 5 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row boundary registers 0-4 each register N indicates amount of memory in rows 0-N (each row is 64 bits wide); the fifth row of memory (if implemented) must contain either 8M or 16M, depending on system configuration boundary register 4 (offset 64h) contains the total system memory, which may not exceed 128M 65h BYTE ??? 66h BYTE PIRQ route control register 0 67h BYTE PIRQ route control register 1 68h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. memory hole register 69h BYTE top of memory 6Ah 6 BYTEs ??? 70h BYTE SMRAM control register 71h 47 BYTEs unused??? A0h BYTE SMI control register A1h BYTE ??? A2h WORD SMI enable register A4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. system event enable A8h BYTE fast off timer register A9h BYTE ??? AAh WORD SMI request register ACh BYTE clock throttle STPCLK# low timer ADh BYTE unused??? AEh BYTE clock throttle STPCLK# high timer AFh BYTE ??? B0h 80 BYTEs unused??? SeeAlso: #00878,#01063,#01055,#01108,#01167 Bitfields for Intel 82425EX PCI control register: Bit(s) Description (Table 01084) 0 CPU-to-PCI byte merging 1 CPU-to-PCI bursting enable 2 PCI posted-write buffer enable 4-3 subtractive decode sampling point 00 slow 01 typical 10 fast 11 reserved 5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. parity error enable 6 target abort error enable 7 reserved SeeAlso: #01083,#01085,#01086,#01087 Bitfields for Intel 82425EX host device control register: Bit(s) Description (Table 01085) 0 HRDY# maximum signal sampling point 0 slow timing 1 fast timing 1 HDEV# signal sampling point 0 slow timing 1 fast timing 2 host device present 7-3 reserved SeeAlso: #01083,#01084 Bitfields for Intel 82425EX local-bus IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. control register: Bit(s) Description (Table 01086) 1-0 primary/secondary PCI IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. enable 00 IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. disabled 01 primary (ports 01F0h-01F7h,03F6,03F7h) 10 secondary (ports 0170h-017Fh,0376h,0377h) 11 reserved 3-2 fast timing bank drive select 1 bit 2 = drive 0 enabled bit 3 = drive 1 enabled 5-4 IORDY sample point Enable Drive Select bit 4 = drive 0 enabled bit 5 = drive 1 enabled 7-6 reserved 9-8 IORDY sample point 00 6 clocks 01 5 clocks 10 4 clocks 11 3 clocks 12-10 recover time (000 = 8 PCI clocks, 001 = 7, ..., 101 = 3, 110/111 = 3) 15-13 reserved SeeAlso: #01083,#01084 Bitfields for Intel chipset ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. I/O recovery timer register: Bit(s) Description (Table 01087) 7 (82425EX/82371) DMAsee Direct Memory Access reserved page register aliasing disable =0 ports 0090h-009Fh alias ports 0080h-008Fh =1 ports 0090h-009Fh forwarded to ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. bus 6 8-bit I/O recovery enable 5-3 8-bit I/O recovery time 000 = 8 SYSCLKs 001-110 = 1-7 SYSCLKs 2 16-bit I/O recovery enable 1-0 16-bit I/O recovery time 00 = 4 SYSCLKs 01-11 = 1-3 SYSCLKs SeeAlso: #01064,#01083,#01084,#01167,#01170 Bitfields for Intel 82425EX part revision register: Bit(s) Description (Table 01088) 7-5 fabrication house identifier (read-only) 4 E0000h-EFFFFh ISA-to-main-memory forwarding enabled 3-0 revision ID (read-only) SeeAlso: #01083,#01089 Bitfields for Intel 82425EX/82371 X-bus Chip Select A register: Bit(s) Description (Table 01089) 7 extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. enabled at FFF80000h-FFFDFFFFh 6 lower (E000h) BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. enabled 5 trigger IRQ13 on FERR# 4 IRQ12 mouse function enabled 3 (82371AB only) alias accesses to PORTs 63h/65h/67h to 61h (else) reserved (0) 2 BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. memory write protect 1 keyboard controller addresses (60h,62h,64h,66h) enabled 0 RTCsee Real-Time Clock addresses (70h-77h) enabled SeeAlso: #01083,#01167,#01088,#01102 Format of PCI Configuration Data for Intel 82380AB PCI-ISA Bridge: Offset Size Description (Table 01090) 00h 64 BYTEs header (see #00878) (vender ID 8086h, device ID 123Ch) 40h BYTE I/O Recovery Register (see #01091) 41h BYTE reserved 42h BYTE MISA Error Status (see #01092) 43h 189 BYTEs reserved SeeAlso: #00873,#01093 Bitfields for Intel 82380AB I/O Recovery Register: Bit(s) Description (Table 01091) 7 SYSCLK select 0 SYSCLK = PCICLK/4 1 SYSCLK = PCICLK/3 6 enable 8-bit I/O recovery 5-3 additional recovery time for 8-bit I/O cycles, in SYSCLKs 2 enable 16-bit I/O recovery 1-0 additional recovery time for 16-bit I/O cycles, in SYSCLKs SeeAlso: #01090 Bitfields for Intel 82380AB MISA error status: Bit(s) Description (Table 01092) 7-3 reserved 2 IOCHK# asserted 1 reserved 0 illegal byte lane combination for PCI I/O detected SeeAlso: #01090 Format of PCI Configuration data for Intel 82380FB PCI-PCI Bridge (MPCI2): Offset Size Description (Table 01093) 00h 64 BYTEs header type 1 [bridge] (see #00878) (vendor ID 8086h, device ID 124Bh) 40h BYTE Connector Control (see #01094) 41h BYTE Connector Event (see #01095) 42h 2 BYTEs reserved 44h WORD Serial Bus Interface/Burst Enable (see #01096) 46h BYTE MPCI2 Miscellaneous Status (see #01097) 47h 5 BYTEs reserved 4Ch WORD Special Message Encode encoded message portion of Special Cycle forwarded by MPCI2 4Eh 178 BYTEs reserved SeeAlso: #00873,#01090 Bitfields for Intel 82380FB Connector Control register: Bit(s) Description (Table 01094) 7-4 reserved 3 QEN2 output signal 2 QEN1 output signal 1-0 reserved SeeAlso: #01093 Bitfields for Intel 82380FB Connector Event register: Bit(s) Description (Table 01095) 7 reserved (1) 6 activate power-no suspend 5 (read-only) inverted state of MISAEN pin 4 (read-only) inverted state of DSTYP pin 3 undocking permit software should set this bit for at least 32 microseconds; when this bit is then cleared, the MPCI2 pulses the OPENACK signal for 256 us to tell external hardware to "eject" the notebook 2 reserved (1) 1 system is docked 0 open requested SeeAlso: #01093 Bitfields for Intel 82380FB Serial Interface/Burst Enable register: Bit(s) Description (Table 01096) 15-13 reserved 12 enable SERR# on discarding of posted write data 11 reserved 10 SDATA signal direction (0 = output, 1 = input) 9 enable write posting 8 enable read bursting 7 enable upstream blind prefetching 6 reserved 5 SDATA signal state (read when bit 10 set, write when bit 10 clear) 4 SDIN signal state 3 do not pulse P_SERR# when S_PERR# is asserted 2 cascade/frame determination delay (0 = 20 P_CLKs, 1 = 10 P_CLKs) 1 serial EEPROM chip select 0 serial EEPROM clock SeeAlso: #01093 Bitfields for Intel 82380FB MPCI2 Miscellaneous Status register: Bit(s) Description (Table 01097) 7-1 reserved 0 (write-clear) P_SERR# was asserted due to invalidation of posted write SeeAlso: #01093 Format of PCI Configuration Data for Intel 82439HX: Offset Size Description (Table 01098) 00h 64 BYTEs header (see #00878) (vender ID 8086h, device ID 1250h) (revision ID 00h = A0 stepping) 40h 16 BYTEs reserved 50h BYTE PCI Control (see #01110) 51h BYTE reserved 52h BYTE cache control (see #01112) 53h 3 BYTEs reserved 56h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. extended control (see #01115) 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. control (see #01116) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. timing (see #01117) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 8 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-7 each register N indicates cumulative amount of memory in rows 0-N (each 64 bits wide), in 4M units 68h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type (see #01119) bits 0-7 indicate whether each row 0-7 contains EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. instead of page-mode DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 69h BYTE ??? 6Ah 8 BYTEs reserved 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. control (see #01123) 73h 29 BYTEs reserved 90h BYTE Error Command (see #01126) 91h BYTE Error Status (see #01127) (read-only) 92h BYTE Error Syndrome (read-only) latest non-zero ECC error syndrome 93h 109 BYTEs reserved SeeAlso: #01108,#01229 Format of PCI Configuration Data for Intel 82439TX "MTXC": Offset Size Description (Table 01099) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7100h) (revision ID 00h = A0 stepping) 40h 15 BYTEs reserved 4Fh BYTE Arbitration Control register (see #01109) 50h BYTE PCI Control register (see #01110) 51h BYTE reserved 52h BYTE CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register (see #01112) 53h BYTE Extended CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register (see #01113) 54h WORD SDRAM Control Register (see #01114) 56h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Extended Control register (see #01115) 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control register (see #01116) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing register (see #01117) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 6 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-5 each register N indicates cumulative amount of memory in rows 0-N (each 64 bits wide), in 4M units 66h BYTE reserved 67h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type High register (see #01213) 68h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type Low register (see #01119) 69h 7 BYTEs reserved 70h BYTE Multi-Transaction Timer register number of PCLKs guaranteed to the current agent before the 82439TX will grant the bus to another PCI agent on request 71h BYTE Extended System Management RAM(Random Access Memory) See also DRAM, SRAM. Control register (see #01149) 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. Control register (see #01123) 73h 6 BYTEs reserved 79h BYTE Miscellaneous Control register (see #01128) 7Ah 134 BYTEs reserved Note: The Intel 82439TX chipset uses PCI configuration mechanism #1 SeeAlso: #00873,PORTIBM PC Portable (uses same BIOS as XT) 0CF8h Format of PCI Configuration Data for Intel 82371AB (PIIX4), ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Bridge: Offset Size Description (Table 01100) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7110h) 40h 12 BYTEs reserved 4Ch BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. I/O recovery timer (see #01101) 4Dh BYTE reserved 4Eh WORD X-Bus Chip Select (see #01089,#01102) 50h 16 BYTEs reserved 60h BYTE PIRQA route control (see #01076) 61h BYTE PIRQB route control (see #01076) 62h BYTE PIRQC route control (see #01076) 63h BYTE PIRQD route control (see #01076) !!!intel\29056201.pdf p.59 64h BYTE serial IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. control 65h 4 BYTEs reserved??? 69h BYTE top of memory 6Ah WORD miscellaneous status 6Ch 10 BYTEs reserved??? 76h BYTE motherboard device DMAsee Direct Memory Access control 0 77h BYTE motherboard device DMAsee Direct Memory Access control 1 78h 9 BYTEs reserved??? 80h BYTE APIC base address relocation 81h BYTE reserved??? 82h BYTE deterministic latency control 83h 13 BYTEs reserved??? 90h WORD PCI DMAsee Direct Memory Access configuration 92h WORD distributed DMAsee Direct Memory Access (channels 0-3) slave base pointer 94h WORD distributed DMAsee Direct Memory Access (channels 5-7) slave base pointer 96h 26 BYTEs reserved??? B0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. general configuration B4h 23 BYTEs reserved??? CBh BYTE real-time clock configuration CCh 52 BYTEs reserved SeeAlso: #00873,#01103,#01104,#01105 Bitfields for Intel PIIX4 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. I/O recovery timer: Bit(s) Description (Table 01101) 7 disable aliasing PORTs 90h-9Fh into 80h-8Fh (except PORTIBM PC Portable (uses same BIOS as XT) 0092h) 6 enable 8-bit I/O recover timer in bits 5-3 5-3 additional 8-bit I/O recovery time (added to 3.5 SYSCLK minimum) 000 = 8 SYSCLKs, else N SYSCLKs 2 enable 16-bit I/O recovery timer in bits 1-0 1-0 additional 16-bit I/O recovery time (added to 3.5 SYSCLK minimum) 00 = 3 SYSCLKs 01 = 1 SYSCLK 10 = 2 SYSCLKs 11 = 4 SYSCLKs SeeAlso: #01100 Bitfields for Intel 82371 X-Bus Chip Select Enable (high byte): Bit(s) Description (Table 01102) 7-3 reserved 2 (82371AB) enable positive PCI decode for Micro Controller at PORTs 62h and 66h 1 (82371AB) enable one-megabyte extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. (FFF00000h-FFF7FFFFh are forwarded to ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. bus, aliased to top of 16M region) 0 enable I/O APIC SeeAlso: #01089 Format of PCI Configuration Data for Intel 82371AB (PIIX4), IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. Controller: Offset Size Description (Table 01103) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7111h) 20h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O base address (for 16 contiguous PORTs) !!!intel\29056201.pdf p.89 40h WORD primary channel timing register 42h WORD secondary channel timing register 44h BYTE slave IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing 45h 3 BYTEs reserved??? 48h BYTE Ultra DMAsee Direct Memory Access/33 control 49h BYTE reserved??? 4Ah WORD Ultra DMAsee Direct Memory Access/33 timing 4Ch 180 BYTEs reserved SeeAlso: #00873,#01100,#01104,#01105 Format of PCI Configuration Data for Intel 82371AB (PIIX4), USBsee Universal Serial Bus Controller: Offset Size Description (Table 01104) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7112h) 20h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O base address (for 32 contiguous PORTs) !!!intel\29056201.pdf p.102 40h 32 BYTEs reserved 60h BYTE USBsee Universal Serial Bus specification release number 00h pre-release 1.0 10h release 1.0 61h 95 BYTEs reserved C0h WORD legacy support C2h 61 BYTEs reserved FFh BYTE miscellaneous support SeeAlso: #00873,#01100,#01103,#01105 Format of PCI Configuration Data for Intel 82371AB (PIIX4), Power Management: Offset Size Description (Table 01105) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7113h) 40h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. base address of power-management I/O ports (same format as PCI base addresses; low bit hardwired to 1) 44h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. initial counts of device 0-11 idle timers 48h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. !!!intel\29056201.pdf p.117 4Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. general-purpose input control 50h 3 BYTEs "device resource D" 53h BYTE unused??? 54h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. device activity event selection A 58h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. device activity event selection B 5Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. "device resource A" 60h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. "device resource B" 64h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. "device resource C" 68h 3 BYTEs "device resource E" 6Bh 5 BYTEs unused??? 70h 3 BYTEs "device resource G" 73h BYTE unused??? 74h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. "device resource H" 78h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. "device resource I" 7Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. "device resource J" 80h BYTE miscellaneous power management 81h 15 BYTEs unused??? 90h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. base address for SMBus(System Management Bus) A derivative of the I2C bus used for communication between various components of a computer, such as smart batteries and their chargers. In contrast to I2C, SMBus specifies fixed voltage levels (instead of relative to the power supply voltage) and a 10 KHz minimum clock rate (I2C minimum is 0). SMBus also specifies several timings which are not required by I2C. See also I2C, ACCESS.bus. I/O ports (same format as PCI base addresses; low bit hardwired to 1) 94h ... D2h BYTE SMBus(System Management Bus) A derivative of the I2C bus used for communication between various components of a computer, such as smart batteries and their chargers. In contrast to I2C, SMBus specifies fixed voltage levels (instead of relative to the power supply voltage) and a 10 KHz minimum clock rate (I2C minimum is 0). SMBus also specifies several timings which are not required by I2C. See also I2C, ACCESS.bus. host configuration D3h BYTE SMBus(System Management Bus) A derivative of the I2C bus used for communication between various components of a computer, such as smart batteries and their chargers. In contrast to I2C, SMBus specifies fixed voltage levels (instead of relative to the power supply voltage) and a 10 KHz minimum clock rate (I2C minimum is 0). SMBus also specifies several timings which are not required by I2C. See also I2C, ACCESS.bus. slave command D4h BYTE SMBus(System Management Bus) A derivative of the I2C bus used for communication between various components of a computer, such as smart batteries and their chargers. In contrast to I2C, SMBus specifies fixed voltage levels (instead of relative to the power supply voltage) and a 10 KHz minimum clock rate (I2C minimum is 0). SMBus also specifies several timings which are not required by I2C. See also I2C, ACCESS.bus. slave shadow port 1 address D5h BYTE SMBus(System Management Bus) A derivative of the I2C bus used for communication between various components of a computer, such as smart batteries and their chargers. In contrast to I2C, SMBus specifies fixed voltage levels (instead of relative to the power supply voltage) and a 10 KHz minimum clock rate (I2C minimum is 0). SMBus also specifies several timings which are not required by I2C. See also I2C, ACCESS.bus. slave shadow port 2 address D6h BYTE SMBus(System Management Bus) A derivative of the I2C bus used for communication between various components of a computer, such as smart batteries and their chargers. In contrast to I2C, SMBus specifies fixed voltage levels (instead of relative to the power supply voltage) and a 10 KHz minimum clock rate (I2C minimum is 0). SMBus also specifies several timings which are not required by I2C. See also I2C, ACCESS.bus. revision D7h SeeAlso: #00873,#01100,#01103,#01104 Format of PCI Configuration Data for Intel 82437MX: Offset Size Description (Table 01106) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 1235h) 40h 16 BYTEs reserved 50h BYTE PCI Control (see #01111) 51h BYTE reserved 52h BYTE cache control (see #01112) 53h 4 BYTEs reserved 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control (see #01116) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. timing (see #01117) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 4 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary Registers 0-3 each register N indicates cumulative amount of memory in rows 0-N, in 4M units (each row is 64 bits wide) 64h 4 BYTEs reserved 68h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type (see #01121) 69h 9 BYTEs reserved 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. control (see #01123) 73h 141 BYTEs reserved SeeAlso: #01108,#01107 Format of PCI Configuration Data for Intel 82437FX: Offset Size Description (Table 01107) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 122Dh) (see #00873) 40h 16 BYTEs reserved 50h BYTE PCI Control (see #01111) 51h BYTE reserved 52h BYTE cache control (see #01112) 53h 4 BYTEs reserved 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control (see #01116) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. timing (see #01117) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 5 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary Registers 0-4 each register N indicates cumulative amount of memory in rows 0-N, in 4M units (each row is 64 bits wide) 65h 3 BYTEs reserved 68h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type (see #01121) 69h 9 BYTEs reserved 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. control (see #01123) 73h 141 BYTEs reserved SeeAlso: #01106,#01108 Format of PCI Configuration Data for Intel 82437VX: Offset Size Description (Table 01108) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7030h) (revision ID 00h = A0 stepping) 40h 15 BYTEs reserved 4Fh BYTE arbitration control (see #01109) 50h BYTE PCI Control (see #01110) 51h BYTE reserved 52h BYTE cache control (see #01112) 53h BYTE cache control extensions (see #01113) 54h WORD SDRAM control (see #01114) 55h BYTE reserved 56h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. extended control (see #01115) 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. control (see #01116) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. timing (see #01117) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 5 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-4 each register N indicates amount of memory in rows 0-N in 4M units (each row is 64 bits wide); the fifth row of memory (if implemented) must contain either 8M or 16M, depending on system configuration boundary register 4 (offset 64h) contains the total system memory, which may not exceed 128M 65h 2 BYTEs reserved 67h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type (high) defines memory type in DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row 4 in bits 4,0 (see #01119) 68h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type (low) (see #01119) 69h BYTE PCI TRDY timer (see #01122) 6Ah 6 BYTEs reserved 70h BYTE Multi-Transaction Timer number of PCLKs guaranteed to the current agent before the 82437 will grant the bus to another PCI agent on request 71h BYTE reserved 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. control (see #01123) 73h BYTE shared memory buffer control (see #01124) 74h BYTE shared memory buffer start address, in 0.5MB units end address is top-of-memory at offset 64h or start of an enabled PCI memory hole when top-of-memory is 16M 76h 2 BYTEs reserved 78h BYTE graphics controller latency timers (see #01125) 79h 135 BYTEs reserved SeeAlso: #00873,#01063,#01083,#01098,#01106 Bitfields for Intel 82437VX,82439TX Arbitration Control register: Bit(s) Description (Table 01109) 7 extended CPU-to-PIIX PHLDA# signalling enabled 6-0 (82439TX) reserved 6-4 reserved 3 (82437VX) CPU(Central Processing Unit) The microprocessor which executes programs on your computer. priority enable =1 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. gets PCI bus after two PCI slots =0 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. gets PCI bus after three PCI slots 2-0 reserved SeeAlso: #01099,#01108,#01110 Bitfields for Intel 82437VX,82439HX/TX PCI Control register: Bit(s) Description (Table 01110) 7-4 reserved (82437VX,82439TX) 7 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. ECC/Parity Select (82439HX) =1 ECC =0 parity 6 ECC TEST enable (82439HX) 5 shutdown to port 92h (82439HX) =1 send 01h to PORTIBM PC Portable (uses same BIOS as XT) 0092h on Shutdown special cycle on host bus 4 dual-processor NA# enable (82439HX) 3 PCI Concurrency Enable =1 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. can access DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM./L2 during non-PIIX PCI master cycles =0 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. kept off PCI bus during all PCI bus-master cycles 2-0 reserved (82437VX,82439TX) 2 SERR# Output Type (82439HX only) =1 SERR# is actively driven high when negated =0 SERR# is PCI-compatible open-drain output 1 reserved 0 Global TXC Enable (82439HX only) =1 enable new 82439HX features SeeAlso: #01099,#01108,#01098,#01112,#01111 Bitfields for Intel 82437FX/82437MX PCI Control register: Bit(s) Description (Table 01111) 7-5 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. inactivity timer (in PCI Clocks less 1) 4 reserved 3 enable PCI Peer Concurrency =1 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. can access DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM./L2 during non-PIIX PCI master cycles =0 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. kept off PCI bus during all PCI bus-master cycles 2 disable PCI Bursting 1 disable PCI Streaming 0 disable Bus Concurrency SeeAlso: #01106,#01107,#01110 Bitfields for Intel 82437,82439HX/TX cache control register: Bit(s) Description (Table 01112) 7-6 secondary cache size 00 none 01 256K 10 512K 11 reserved 5-4 L2 RAM(Random Access Memory) See also DRAM, SRAM. type 00 pipelined burst SRAM(Static Random Access Memory) RAM which typically consists of one flip-flop per bit of memory. Unlike DRAMs, static RAM retains its contents as long as power is applied. Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip. See also DRAM./DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 01 reserved 10 asynchronous SRAM(Static Random Access Memory) RAM which typically consists of one flip-flop per bit of memory. Unlike DRAMs, static RAM retains its contents as long as power is applied. Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip. See also DRAM. (82437FX/MX/VX,82439TX only) 11 two banks of pipelined burst cache 3 NA disable =1 never assert NA# pin 2 reserved (82437FX/MX/VX,82439TX) 2 Extended Cacheability Enable (82439HX) =1 cache up to 512M =0 cache only first 64M 1 Secondary CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Force Miss or Invalidate =1 force all memory accesses to bypass L2 cache 0 First Level CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Enable =1 all memory accesses made non-cacheable by CPU(Central Processing Unit) The microprocessor which executes programs on your computer. L1 cache SeeAlso: #01099,#01108,#01098,#01110,#01113,#01114,#01106 Bitfields for Intel 82437VX,82439TX cache control extensions register: Bit(s) Description (Table 01113) 7-6 reserved 5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. cache detected (read-only) 4-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. cache refresh timer number of HCLKs 82437VX,82439TX remains idle during DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. cache refresh SeeAlso: #01099,#01108,#01112 Bitfields for Intel 82437VX,82439TX SDRAM control register: Bit(s) Description (Table 01114) 15-9 reserved 8-6 Special SDRAM Mode Select 000 normal mode (default) 001 enable NOP command 010 enable All Banks Precharge command 011 enable Mode Register Command 100 enable CBR Cycle 101 reserved 11x reserved 5 (82437VX) reserved 5 (82439TX) RAS# to CASsee Communicating Applications Specification# Override =1 and CASsee Communicating Applications Specification# latency=0, RAS# to CASsee Communicating Applications Specification# is delayed 2 HCLKs =0 RAS# to CASsee Communicating Applications Specification# delay determined solely by CASsee Communicating Applications Specification# latency setting 4 CASsee Communicating Applications Specification# latency =1 latency is 2 for all SDRAM cycles =0 latency is 3 3 RAS# precharge and refresh timing =0 slower =1 faster 2 reserved 1 (82437VX) reserved 1 (82439TX) 64-Mbit Technology Enable =1 supports 64M-bit SDRAM devices =0 supports 64M-bit EDO/FPM devices only 0 reserved SeeAlso: #01099,#01108,#01112 Bitfields for Intel 82437VX,82439HX/TX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. extended control register: Bit(s) Description (Table 01115) 7 reserved 6 (VX/TX) refresh RAS# assertion length (0=4 clocks, 1=5 clocks) 5 (VX/TX) Fast EDO Path Select 4 Speculative Leadoff Disable 3 (82439HX) Turn-Around Insertion Enable =1 insert one extra clock of turnaround time after asserting MWE# 2-1 Memory Address Drive Strength 82437VX: 82439HX: 82439TX: 00 reserved 00 8mA 00 10mA/10mA (MA/MWE#) 01 10mA (default) 01 8mA/12mA (MAA/MWE#) 01 10mA/16mA (MA/MWE#) 10 16mA 10 12mA/8mA (MAA/MWE#) 10 16mA/10mA (MA/MWE#) 11 reserved 11 12mA 11 16mA/16mA (MA/MWE#) 0 (82437VX) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Symmetry Detect Mode (used to force some memory address lines to fixed value for detecting DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. symmetry row-by-row) 0 (82439HX) 64MBit Mode Enable =1 enable support for 64M SIMMs 0 (82439TX) reserved SeeAlso: #01099,#01108,#01098,#01116 Bitfields for Intel 82437,82439HX/TX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. control register: Bit(s) Description (Table 01116) 7-6 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Hole Enable 00 none 01 512K-640K 10 15M-16M (82437FX/MX/VX only) 11 14M-16M (82437VX,82439TX only) 5 reserved 4 (82437MX only) refresh type during Suspend =1 self-refreshing DRAMs in system =0 CAS-before-RAS refresh (82439TX only) Enhanced Paging disabled 3 EDO Detect Mode enable (used to detect whether memory is EDO bank-by-bank) 2-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. refresh rate FX/VX/HX MX TX 000 disabled 15.6 us disabled 001 50 MHz 31.2 us 15.6 us 010 60 MHz 62.4 us 31.2 us 011 66 MHz 125 us 64.4 us 100 reserved 250 us 125 us 101 reserved reserved 256 us 1xx reserved reserved reserved SeeAlso: #01099,#01108,#01098,#01115,#01106 Bitfields for Intel 82437FX/MX/VX,82439HX/TX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. timing register: Bit(s) Description (Table 01117) 7 (82437FX,82439TX) reserved 7 (82437MX) MA[11:2] buffer strength =0 8mA =1 12mA 7 (82437VX) MA-to-RAS# Delay =1 one clock =0 two clocks 7 (82439HX) Turbo Read Leadoff =1 bypass first register in DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. data pipeline, saving one clock (may only be set in a cacheless configuration) 6-5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Read Burst Timing 00 x444 (EDO and Standard Page Mode) 01 x333 (EDO), x444 (SPM) 10 x222 (EDO), x333 (SPM) 11 x322 (EDO), x333 (SPM) (82437VX only) 11 reserved (other) 4-3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Write Burst Timing 00 x444 01 x333 10 x222 11 reserved 2 (82439TX) reserved 2 RAS-to-CAS Delay =1 two clocks =0 three clocks 1-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Leadoff Timing 82437FX/MX Read Leadoff Write Leadoff RAS# Precharge 00 8 6 3 01 7 5 3 10 8 6 4 11 7 5 4 82437VX,82439TX Read Write Leadoff RAS# Precharge 00 11 7 3 01 10 6 3 10 11 7 4 11 10 6 4 82439HX Read Leadoff Write Leadoff RAS# Precharge 00 7 6 3 01 6 5 3 10 7 6 4 11 6 5 4 SeeAlso: #01099,#01108,#01116,#01106,#01107 Bitfields for Intel 8243x/8244x Programmable Attribute Map Register: Bit(s) Description (Table 01118) 7 reserved 6 cache enable (region 1) 5 write enable (region 1) 4 read enable (region 1) 3 reserved 2 cache enable (region 0) 1 write enable (region 0) 0 read enable (region 0) Notes: each programmable attribute map register controls two memory regions at the top of the first megabyte of memory for the Intel 82441FX and 82443BX/LX, bits 6 and 2 are reserved, as cacheability is set using the Pentium Pro/II/Celeron's MTRR registers (see MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 000000FEh) Intel 82434,82437FX/MX/VX,82439HX,82441FX,82443EX/LX PAM registers/regions: PAM0 low: reserved [*] PAM0 hi: segment F000-FFFF PAM1 low: segment C000-C3FF PAM1 hi: segment C400-C7FF PAM2 low: segment C800-CBFF PAM2 hi: segment CC00-CFFF PAM3 low: segment D000-D3FF PAM3 hi: segment D400-D7FF PAM4 low: segment D800-DBFF PAM4 hi: segment DC00-DFFF PAM5 low: segment E000-E3FF PAM5 hi: segment E400-E7FF PAM6 low: segment E800-EBFF PAM6 hi: segment EC00-EFFF [*] on the 82434 (and possibly other Intel chipsets), the low nybble of PAM0 controls segment 8000-9FFF SeeAlso: #01055,#01108,#01098,#01099,#01229,#01106,#01107,#01142,#01129 Bitfields for Intel 82437VX,82439TX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type register: Bit(s) Description (Table 01119) 7,3 row 3 type 6,2 row 2 type 5,1 row 1 type 4,0 row 0 type 00 SPM DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 01 EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 10 SDRAM 11 reserved SeeAlso: #01099,#01108,#01118,#01213 Bitfields for Intel 82439TX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type high register: Bit(s) Description (Table 01213) 7 Host Frequency detection =1 66MHz Bus =0 60MHz bus 5,1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row 5 type 4,0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. ROW 4 type 00 SPM 01 EDO 10 SDRAM 11 reserved 6,3 reserved 2 Memory Address select Enabled SeeAlso: #01099,#01119 Bitfields for Intel 82437FX/82437MX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type register: Bit(s) Description (Table 01121) 7-4 reserved 3-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row N is EDO instead of page-mode DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. SeeAlso: #01106,#01107 Bitfields for Intel 82437VX PCI TRDY timer: Bit(s) Description (Table 01122) 7-3 reserved 2-0 TRDY timeout value 000 2 PCICLKs 001 4 PCICLKs 010 6 PCICLKs 011 8 PCICLKs 1xx reserved SeeAlso: #01108,#01123 Bitfields for Intel 82437,82439HX/TX,82443BX/EX/LX SMRAM control register: Bit(s) Description (Table 01123) 7 reserved 6 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Space Open =1 make SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. visible even when not in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. if bit 4 =0 5 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Space Closed =1 no data references permitted to SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. even in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. 4 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Space Locked =1 force bits 4 and 6 to become read-only; and clear bit 6 3 SMRAM Enable =1 128K DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. are accessible for use at A000 while in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. 2-0 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Space Base Segment 010 segment A000-BFFF 100 segment C000-CFFF (82437MX,82443EX only) other reserved Note: bits 5 and 6 must never both be set at the same time SeeAlso: #01099,#01108,#01098,#01124,#01106,#01107,#01142,#01129 Bitfields for Intel 82437VX Shared Memory Buffer control register: Bit(s) Description (Table 01124) 7-2 reserved 1 enable shared memory buffer 0 redirect shared memory buffer access =0 treat SMB area as a hole in system DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. SeeAlso: #01108,#01123,#01125 Bitfields for Intel 82437VX Graphics Controller Latency Timer: Bit(s) Description (Table 01125) 7-6 reserved 5-3 GC latency for PCI reads (in 4 HCLK multiples) (default=100) 2-0 GC latency for CPU(Central Processing Unit) The microprocessor which executes programs on your computer. and PCI writes (in 4 HCLK multiples) (default=011) SeeAlso: #01108,#01124 Bitfields for Intel 82439HX Error Command register: Bit(s) Description (Table 01126) 7 SERR# duration =0 one PCI clock =1 until error flags are cleared 6-3 reserved 2 force bad parity on multiple-bit uncorrectable error 1 assert SERR# on multiple-bit uncorrectable error 0 assert SERR# on single-bit correctable error SeeAlso: #01098,#01127 Bitfields for Intel 82439HX Error Status register: Bit(s) Description (Table 01127) 7-5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row associated with multi-bit error 4 multi-bit uncorrectable error occurred (write 1 bit to clear) 3-1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row associated with single-bit correctable error 0 single-bit correctable error occurred (write 1 bit to clear) SeeAlso: #01098,#01126 Bitfields for Intel 82439TX miscellaneous control register: Bit(s) Description (Table 01128) 7 reserved 6 ACPI control register enable 5 Suspend refresh type (EDO/FPM DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. only) =1 Self refresh (Always for SDRAM) =0 CBR refresh 4 Normal refresh enable When set to 1, 82439TX switches from suspend refresh to normal refresh 3 reserved 2 Internal clock control disable =1 disable =0 enable Disables 82439TX internal clocks during suspend, reducing power consumption. 1-0 reserved SeeAlso: #01099 Format of PCI configuration for Intel 82443EX/LX Device 0 (Host-PCI): Offset Size Description (Table 01129) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7180h) chipset is 82443EX if revision >= 03h 40h 16 BYTEs reserved 50h WORD PAC Configuration register (See #01131) 52h BYTE reserved 53h BYTE Data Buffer Control register (see #01132) 54h BYTE reserved 55h WORD DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type register (see #01133) 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control register (see #01134) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing register (see #01135) 59h 7 BYTEs PAM Configuration registers 0-6 (See #01118) 60h 8 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-7 each register indicates top of memory for a particular row, in 8MB units; DIMMs use two rows each, with single-sided DIMMs leaving the odd-numbered rows unpopulated 68h BYTE Fixed DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Hole Control register (see #01147) 69h BYTE reserved 6Ah WORD DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Extended Mode Select register (see #01136) 6Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Memory Buffer Strength Control register (see #01137) 70h BYTE Multi-Transaction Timer register (see #01140) 71h BYTE reserved 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. Control register (see #01123) 73h 29 BYTEs reserved 90h BYTE Error Command register (see #01156) 91h BYTE Error Status 0 register (see #01138) 92h BYTE Error Status 1 register (see #01139) 93h BYTE Reset Control Register (see #01239) 94h 12 BYTEs reserved A0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Capability register (see #01158) A4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Status register (see #01159) A8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Command register (see #01160) ACh 4 BYTEs reserved B0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Control register (see #01161) B4h BYTE Arpeture Size Control register (see #01162) B5h 3 BYTEs reserved B8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Arpeture Translation Table Base register (see #01163) BCh BYTE AGP MTT Control register (see #01140) BDh BYTE AGP Low Priority Transaction timer register (see #01141) BCh 67 BYTEs reserved Notes: The 82443EX is virtually identical to the 82443LX, except that it does not support ECC type DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM.. The Intel 82443EX/LX chipsets use PCI configuration mechanism #1 SeeAlso: #01130,#01142,PORTIBM PC Portable (uses same BIOS as XT) 0CF8h Format of PCI configuration for Intel 82443EX/LX Device 1 (PCI-PCI): Offset Size Description (Table 01130) 00h 64 BYTEs header, type 1 [bridge] (see #00878) (vendor ID 8086h, device ID 7181h) chipset is 82443EX if revision >= 03h 40h 192 BYTEs reserved Note: The Intel 82443LX chipset uses PCI configuration mechanism #1 SeeAlso: #01129,#01143,PORTIBM PC Portable (uses same BIOS as XT) 0CF8h Bitfields for Intel 82443EX/LX (Device 0) PAC Configuration register: Bit(s) Description (Table 01131) 15 WSC# Handshake Disable 14 (82443LX) Host Frequency (read-only) =1 60MHz =0 66MHz 14 (82443EX) reserved 13-12 reserved 11 ??? (Not documented by Intel!) 10 PCI Agent to Arperture Access Disable 9 Aperture Access Global Enable 8-6 (82443EX) reserved 8-7 (82443LX) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Data Integrety Mode 00 Non-ECC (no check, no correct) 01 EC-only (do check, no correct) 10 reserved 11 ECC (do check, do correct) 6 (82443LX) ECC-Test Diagnostic Mode Enabled 5 MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. Present Note: Controls routing of Monochrome Display Adaptor I/O and memory range accesses. Works in conjunction with the VGA-bit in Bridge Control register of device 1 (see #00901): VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. 0 0 MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. and VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. routed to PCI bus 0 1 reserved 1 0 MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. and VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. routed to AGP bus 1 1 VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. routed to AGP bus, MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. routed to PCI bus 4-0 reserved SeeAlso: #00901,#01129 Bitfields for Intel 82443EX/LX (Device 0) Data Buffer Control register: Bit(s) Description (Table 01132) 7 reserved 6 CPU-to-PCI posting enabled 5 Write post during I/O Bridge access enabled 4-0 reserved SeeAlso: #01129 Bitfields for Intel 82443EX/LX (Device 0) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type register: Bit(s) Description (Table 01133) 15-14 row 7 type 0 0 EDO (Same values for each row) 0 1 reserved 1 0 SDRAM 1 1 empty row 13-12 row 6 type 11-10 row 5 type 9-8 row 4 type 7-6 row 3 type 5-4 row 2 type 3-2 row 1 type 1-0 row 0 type SeeAlso: #01129,#01134 Bitfields for Intel 82443EX/LX (Device 0) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control register: Bit(s) Description (Table 01134) 7-6 reserved 5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. EDO Auto-Detect mode enabled 4 SDRAM power management enabled 3 reserved 2-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. rate 000 = RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. disabled 001 = Normal (Based on PAC Configuration bit 14) 010-111 = reserved SeeAlso: #01129,#01133,#01135 Bitfields for Intel 82443EX/LX (Device 0) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing register: Bit(s) Description (Table 01135) 7 SDRAM RAS to CASsee Communicating Applications Specification Delay (1 = 2 clocks, 0 = 3 clocks) 6 SDRAM CASsee Communicating Applications Specification Latency (1 = 2 clocks, 0 = 3 clocks) 5 SDRAM RAS Precharge Time (1 = 2 clocks, 0 = 3 clocks) 4 EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Read Burst timing =1 Read rate is x222 =0 Read rate is x333 3 EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Write Burst timing =1 Write rate is x222 =0 write rate is x333 2 EDO RAS Precharge Time (1 = 3 clocks, 0 = 4 clocks) 1 EDO RAS to CASsee Communicating Applications Specification Delay (1 = 2 clocks, 0 = 3 clocks) 0 MA Wait State =1 Fast (0 wait states for SDRAM, clocks run normally for EDO) =0 Slow (1 wait state for SDRAM, add one clock to all EDO timings) SeeAlso: #01129,#01134 Bitfields for Intel 82443EX/LX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Extended Mode Select register: Bit(s) Description (Table 01136) 15-8 reserved 7-5 Operating Mode 000 Normal operating mode 001 NOP command enabled 010 All banks precharge enable 011 Mode register set command enable 100 CBR cycle enable 101-11x reserved 4 reserved 3-2 Page timeout select 00 16 clocks 01-11 reserved 1-0 Close both banks control 00 close both banks on page misses 01-11 reserved SeeAlso: #01129 Bitfields for Intel 82443EX/LX Memory Buffer Strength Control register: Bit(s) Description (Table 01137) 31-30 MAA[1-0] buffer strength 00 48mA (same values for bits 25-12,5-0) 01 42mA 10 22mA 11 reserved 29-28 (82443LX only) MECC[7-0] buffer strength 00 42mA (same values for bits 27-26,11-6) 01 38mA 10 33mA 11 reserved 27-26 MD[63-0] buffer strength 25-24 RCSA[0]# & RCSB[0]#/MAB[6] buffer strength 23-22 (82443LX only) MAB[1-0] buffer strength 21-20 MAA[13:2] buffer strength 19-18 RCSA[1]# & RCSB[1]#/MAB[7] buffer strength 17-16 RCSA[2]# & RCSB[2]#/MAB[8] buffer strength 15-14 RCSA[3]# & RCSB[3]#/MAB[9] buffer strength 13-12 (82443LX only) RCSA[4]# & RCSB[4]#/MAB[10] buffer strength 11-10 (82443LX only) CQDB[5,1]# buffer strength 9-8 CQDA[5,1]# buffer strength 7-6 CQDA[7-6,4-2,0]# buffer strength ---82443LX--- 5-4 RCSA[5]# & RCSB[5]#/MAB[11] buffer strength 3-2 RCSA[6]#/MAB[2] & RCSB[6]#/MAB[12] buffer strength 1-0 RCSA[7]#/MAB[3] & RCSB[7]#/MAB[13] buffer strength ---82443EX--- 5-0 reserved SeeAlso: #01129 Bitfields for Intel 82443EX/LX Error Status 0 register: Bit(s) Description (Table 01138) ---82443LX--- 7-5 Multi-bit first error (read-only) Indicates which DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row had the multi-bit error 4 Multiple-bit ECC Error occurred flag 3-1 Single-bit first row error (read-only) Indicates which DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row had the single-bit error 0 Single-bit ECC error occurred flag ---82443EX--- 7-0 reserved Note: Write a 1 to bits 4 & 0 to clear the flags SeeAlso: #01129,#01139 Bitfields for Intel 82443EX/LX Error Status 1 register: Bit(s) Description (Table 01139) 7-3 reserved 2 AGP non-snoopable access outside of graphics arperture 1 AGP non-snoopable access outside of main DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. ranges and arperture 0 access to invalid graphics arperture translation table entry Note: Write a 1 to these bit(s) to clear SeeAlso: #01129,#01138 Bitfields for Intel 82443EX/LX Multi-Transaction Timer register: Bit(s) Description (Table 01140) 7-3 Multi-transaction timer count value 2-0 reserved SeeAlso: #01129,#01141 Bitfields for Intel 82443EX/LX Low Priority Transaction Timer register: Bit(s) Description (Table 01141) 7-3 Low priority transaction timer count value 2-0 reserved SeeAlso: #01129,#01140 Format of PCI Configuration for Intel 82443BX Device 0 (Host-PCI): Offset Size Description (Table 01142) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7190h/7192h) 10h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. graphics aperture base address 2Ch WORD subsystem vendor identification (write-once) 2Eh WORD subsystem device identification (write-once) 40h 16 BYTEs reserved (0) 50h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. 440BX Configuration (see #01144) 54h 3 BYTEs reserved (0) 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control (see #01145) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing (see #01146) 59h 7 BYTEs Programmable Attribute Map register 0-6 (see #01118) 60h 8 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Boundary registers 0-7 each register indicates top of memory for a particular row, in 8MB units; DIMMs use two rows each, with single-sided DIMMs leaving the odd-numbered rows unpopulated 68h BYTE Fixed DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Hole Control (see #01147) 69h 6 BYTEs Memory Buffer Strength Control (see #01148) 6Fh 2 BYTEs reserved (0) 71h BYTE Intel Reserved (1Fh) 72h BYTE SMRAM Control (see #01123) 73h BYTE Extended SMRAM Control (see #01149) 74h WORD SDRAM Row Page Size (see #01150) 76h WORD SDRAM Control Register (see #01151) 78h WORD Paging Policy Register (see #01152) 7Ah BYTE Power Management Control (see #01153) 7Bh WORD Suspend CBR RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Rate Register (see #01154) 7Dh 3 BYTEs reserved (0) 80h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Error Address Pointer (see #01155) 84h 12 BYTEs reserved (0) 90h BYTE Error Command Register (see #01156) 91h WORD Error Status Register (see #01157) 93h BYTE reserved (0) 94h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Intel Reserved (00006104h) 98h WORD Intel Reserved (0500h) 9Ah BYTE Intel Reserved (0) 9Bh 5 BYTEs reserved (0) A0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Capability Identifier (see #01158) A4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Status Register (read-only) (see #01159) A8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Command Register (see #01160) ACh 4 BYTEs reserved (0) B0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. AGP Control Register (see #01161) B4h BYTE Aperture Size Control (see #01162) B5h 3 BYTEs reserved (0) B8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Aperture Translation Table (see #01163) BCh 2 BYTEs reserved BEh WORD reserved (0) C0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Intel Reserved (0) C4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Intel Reserved (0) C8h BYTE Intel Reserved (18h) C9h BYTE Intel Reserved (0Ch) CAh 3 BYTEs Memory Buffer Frequency Select (see #01164) CDh 3 BYTEs reserved (0) D0h 8 BYTEs BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. scratch pad (read-write, init to 0 on reset) D8h 8 BYTEs Intel Reserved (0) E0h 2 DWORDs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Write Thermal Throttling Control (see #01165) E8h 8 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Read Therman Throttling Control (see #01165) F0h WORD Buffer Control Register (see #01166) F2h 2 BYTEs Intel Reserved (0000h) F4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Intel Reserved (0000F800h) bits 30-29 are "Abort Disable Test Mode" configuration bits and should always be set (according to Intel Specification Update) F8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Intel Reserved (00000F20h) FCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Intel Reserved (0) SeeAlso: #00873,#01143,PORTIBM PC Portable (uses same BIOS as XT) 0022h"82443BX" !!!intel\29063301.pdf p.34 Format of PCI Configuration for Intel 82443BX Device 1 (PCI-AGP): Offset Size Description (Table 01143) 00h 64 BYTEs header, type 1 [bridge] (see #00878) (vendor ID 8086h, device ID 7191h) 40h 192 BYTEs reserved SeeAlso: #00873,#01142,#01130 !!!intel\29063301.pdf p.80 Bitfields for Intel 82443BX (Device 0) NBX Configuration Register: Bit(s) Description (Table 01144) 31-24 SDRAM rows without ECC; each set bit indicates a row in the SDRAM array with does NOT have error correction (bit 24 = row 0; note that double- sided DIMMs use two rows, one for the front and one for the back) 23-19 reserved 18 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. data asserted on host bus on the same clock on which the snoop result is sampled, instead of one clock later 17 ECC signals are always driven for EDO memory 16 IDSEL redirection =0 allocate IDSEL1/AD12 to bridge, never assert external AD12 =1 allocate IDSEL7/AD18 to bridge, never assert external AD18; PCI configuration cycles for Bus0/Device7 are redirected to Bus0/Device1 15 disable WSC# handshake (uni-processor mode) 14 Intel Reserved 13:12 Host/DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. frequency 00 100 MHz 01 reserved 10 66 MHz 11 reserved 11 enable AGP-to-PCI access (note: AGP-to-PCI traffic is not allowed to target ISA-bus devices) 10 disable PCI agent access to graphis aperture (ignored if bit 9 clear) 9 global enable graphics aperture access 8:7 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Data Integrity Mode 00 non-ECC 01 error checking only (e.g. parity) 10 ECC mode 11 ECC mdoe with hardware scrubbing 6 enable ECC diagnostics mode (when set, ECC lines are forced to zero on writes and compared to internally-generated ECC on reads) 5 monochrome video adapter present on PCI/ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. bus (with primary adapter on AGP bus) if register 3Eh bit 3 is clear, all VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. cycles are sent to PCI regardless of this bit otherwise: if clear, all VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. cycles are sent to AGP; if set, all VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. cycles except MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. ranges (memory B0000h-B7FFFh and ports 03B4h,03B5h, 03B8h,03B9h,03BAh,03BFh) are sent to AGP 4 reserved 3 enable posting of host USWC (U??? Speculative Write Combine) writes to PCI memory 2 In-Order Queue Depth =1 maximum (PPro supports up to 8, but 82443BX only supports depth 4) =0 depth forced to 1 (no pipelining on processor bus) 1:0 reserved SeeAlso: #01142 Bitfields for 82443BX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control: Bit(s) Description (Table 01145) 7-6 reserved 5 module mode configuration (read-only) =0 self-refresh entry is staggered; if "SDRAMPWR" (offset 76h bit 4) is set, 3 DIMMs are supported, CKE[5:0] is driven, and dynamic SDRAM power-down is available; if "SDRAMPWR" is clear, 4 DIMMs are supported but power-down is not available =1 self-refresh entry is not staggered; 3 DIMMs are supported, only CKE0 is driven, and dynamic power-down is not available 4:3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 00 EDO 01 SDRAM 10 registered SDRAM 11 reserved 2:0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. refresh rate 000 disabled 001 15.6 microseconds 010 31.2 microseconds 011 62.4 100 124.8 101 249.6 else reserved SeeAlso: #01142 Bitfields for Intel 82443BX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing: Bit(s) Description (Table 01146) 7-2 reserved 1 add one EDO RASx# wait state for row misses (two tASR instead of one) 0 add one wait state to first EDO CASx# assertion for page hits (2 Tasc instead of 1 Tasc) SeeAlso: #01142 Bitfields for Intel 82443BX/EX/LX Fixed DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Hole Control: Bit(s) Description (Table 01147) 7-6 Hole Enable 00 none 01 512K-640K 10 15M-16M 11 reserved 5-0 reserved (0) SeeAlso: #01142,#01129 Bitfields for Intel 82443BX Memory Buffer Strength Control: Bit(s) Description (Table 01148) 47-40 reserved (0) 39-38 strengths of MAA[13:0], WEA#, SRASA#, SCASA# (settings same as below) 37-36 strengths of MAB[12:11,9:0], MAB[13,10], WEB#, SRASB#, SCASB# 00 = 1x (at both 66 and 100 MHz) 01 reserved 10 = 2x (at both 66 and 100 MHz) 11 = 3x (at both 66 and 100 MHz) 35-34 MD[63:0] buffer strength control 2 4 DIMM FET config: strength for MD[63:0] path connected to DIMMs 2&3 3/4 DIMM non-FET config: program to same value as buffer str. ctrl 1 33-32 MD[63:0] buffer strength control 1 4 DIMM FET config: strength for MD[63:0] path connected to DIMMs 0&1 3/4 DIMM non-FET config: programmable based on total load detected on all DIMM connectors 00 = 1x (at both 66 and 100 MHz) 01 reserved 10 = 2x (at both 66 and 100 MHz) 11 = 3x (at 100 MHz only) 31-30 MECC[7:0] buffer strength control 2 4 DIMM FET config: strength for MECC[7:0] path connected to DIMMs 2&3 3/4 DIMM non-FET config: program to same value as buffer str. ctrl 1 29-28 MECC[7:0] buffer strength control 1 4 DIMM FET config: strength for MD[63:0] path connected to DIMMs 0&1 3/4 DIMM non-FET config: programmable based on total load detected on all DIMM connectors (values same as for MD[63:0] buffer strength) 27-26 CSB7#/CKE5 buffer strength (same values as bits 37-36) 25-24 CSA7#/CKE3 buffer strength (same values as bits 37-36) 23-22 CSB6#/CKE4 buffer strength (same values as bits 37-36) 21-20 CSA6#/CKE2 buffer strength (same values as bits 37-36) 19 CSA5#/RASA5#, CSB5#/RASB5# buffer strength 0 = 1x (at both 66 and 100 MHz) 1 = 2x (at both 66 and 100 MHz) 18 CSA4#/RASA4#, CSB4#/RASB4# buffer strength (same values as bit 19) 17 CSA3#/RASA3#, CSB3#/RASB3# buffer strength (same values as bit 19) 16 CSA2#/RASA2#, CSB2#/RASB2# buffer strength (same values as bit 19) 15 CSA1#/RASA1#, CSB1#/RASB1# buffer strength (same values as bit 19) 14 CSA0#/RASA0#, CSB0#/RASB0# buffer strength (same values as bit 19) 13-12 DQMA5/CASA5# buffer strength 00 = 1x (at both 66 and 100 MHz) 01 reserved 10 = 2x (at both 66 and 100 MHz) 11 = 3x (at 66 MHz only) 11-10 DQMA1/CASA1# buffer strength (same values as bits 37-36) 9-8 DQMB5/CASB5# buffer strength (same values as bits 13-12) 7-6 DQMB1/CASB1# buffer strength (same values as bits 13-12) 5-4 DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# buffer strength (as for bits 37-36) 3-2 CKE1/GCKE buffer strength (same values as bits 37-36) 1-0 CKE0/FENA buffer strength (same values as bits 37-36) SeeAlso: #01142 Bitfields for Intel 82439TX/82443BX Extended SMRAM Control register: Bit(s) Description (Table 01149) 7 SMRAM location =0 compatible SMRAM space at segment A000h =1 high SMRAM space at addreses 100A0000h to 100FFFFFh (accessing physical DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. addresses A0000h to FFFFFh) 6 (write-clear) access to extended SMRAM memory range when SMRAM space is not open and not in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. 5 enable write-through caching of SMRAM (forced to 1 by 82443BX, to 0 by 82439TX) 4 enable L1 caching of SMRAM (forced to 1 by 82443BX) 3 enable L2 caching of SMRAM (forced to 1 by 82443BX) 2-1 TSEG size (read-only once SMRAM locked) (see #01123) 00 128K 01 256K 10 512K 11 1M 0 enable TSEG (read-only once SMRAM locked) (see #01123) when both SMRAM and TSEG are enabled, the top N kilobytes of physical DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. are no longer claimed by the memory controller, and instead appear as extended SMRAM at an address 256M higher than the physical address SeeAlso: #01142,#01123,#01099 Bitfields for Intel 82443BX SDRAM Row Page Size: Bit(s) Description (Table 01150) 15-14 page size for row 7 (back of DIMM4) 00 two KB 01 four KB 10 eight KB 11 reserved 13-12 page size for row 6 (front of DIMM4) ... 3-2 page size for row 1 (back of DIMM1) 1-0 page size for row 0 (front of DIMM1) SeeAlso: #01142 Bitfields for Intel 82443BX SDRAM Control Register: Bit(s) Description (Table 01151) 15-10 reserved (0) 9-8 add one-clock delay to idle/pipeline DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. leadoff when =01 (all other values are illegal) 7-5 SDRAM mode select 000 normal operation 001 issue NOP command on all CPU-to-SDRAM cycles 010 issue All-Banks-Precharge command on all CPU-to-SDRAM cycles 011 issue mode register set command on CPU-to-SDRAM cycles (command is driven on memory address lines, so the proper address must be calculated for each row of memory to drive the correct command; MAx[2:0] must be driven to 010 for burst-of-4 mode, MAx3 to 1 for interleave wrap type, MAx4 to the value of the CASsee Communicating Applications Specification# latency bit, MAx[6:5] to 01, and MAx[12:7] to 0000000 100 issue CBR cycles on all CPU-to-SDRAM cycles else reserved 4 "SDRAMPWR" specifies how CKE signals are driven for various DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. configurations; refer to #01145 bit 5 3 Leadoff Command Timing =0 four CS# clocks (100 MHz or 66 MHz desktop if MAA/MAB load > 9) =1 three CS# clocks (66 MHz mobile platforms, or desktop w/ load <= 9) 2 CASsee Communicating Applications Specification# latency =0 three DCLKs =1 two DCLKs 1 SDRAM RAS# to CASsee Communicating Applications Specification# delay =0 three clocks =1 two clocks 0 SDRAM RAS# precharge =0 three clocks =1 two clocks SeeAlso: #01142 Bitfields for Intel 82443BX Paging Policy Register: Bit(s) Description (Table 01152) 15-8 banks per row (bit 7 is row 0, bit 15 is row 7) =0 two banks =1 four banks 7-5 reserved 4 Intel Reserved 3-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Idle Timer ("DIT") number of clocks in idle state before all pages are precharged 0000 no clocks 0001 2 clocks 0010 4 clocks 0011 8 clocks 0100 10 clocks 0101 12 clocks 0110 16 clocks 0111 32 clocks 1xxx never (pages are not closed on idle) SeeAlso: #01142 Bitfields for Intel 82443BX Power Management Control Register: Bit(s) Description (Table 01153) 7 enable SDRAM power-down for idle rows 6 enable ACPI control register at PORTIBM PC Portable (uses same BIOS as XT) 0022h 5 suspend refresh type =0 self-refresh =1 CBR mode 4 enable normal refresh (must be set before accessing RAM(Random Access Memory) See also DRAM, SRAM. after a reset) 3 quick-start mode enabled (read-only) 2 enable dynamic clock gating on AGPset "IDLE" condition (all buses in idle state) 1 AGP disabled (read-only) 0 enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reset without PCIRST enable SeeAlso: #01142 Bitfields for Intel 82443BX Suspend CBR RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Rate: Bit(s) Description (Table 01154) 15-13 reserved (0) 12 enable automatic Suspend CBR RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Rate adjustment (based on number of OSCCLKs in a given time); if clear, the below field must be programmed to guarantee minimum refresh rates in the worst case 11-0 Suspend CBR RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Rate (number of OSCCLKs between refresh requests) SeeAlso: #01142 Bitfields for Intel 82443BX Error Address Pointer: Bit(s) Description (Table 01155) 31-12 (read-only) bits 31-12 of address in which first parity/ECC error occurred 11-2 reserved 1 (write-clear) multi-bit error occurred 0 (write-clear) single-bit error occurred SeeAlso: #01156,#01142 Bitfields for Intel 82443BX/EX/LX Error Command Register: Bit(s) Description (Table 01156) 7 enable SERR# on AGP non-snoopable access outside graphics aperture 6 enable SERR# on invalid AGP DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. access (82443BX) enable SERR# on AGP Non-snoopable access to location outside main DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. and arpeture rangles (82443EX/LX) 5 enable SERR# on access to invalid Graphics Aperture Translation Table 4 enable SERR# on receiving Target Abort 3 enable SERR# when Thermal DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Throttling detected (82443BX) enable SERR# on PCI Parity Error (82443EX/LX) ---82443BX--- 2 SERR# mode =0 asserted for one PCI clock =1 level mode signal (for systems that connect SERR# to EXTSMI#) 1 enable SERR# on receiving multi-bit Parity/ECC error 0 enable SERR# on receiving single-bit (corrected) ECC error ---82443EX/LX--- 2-0 reserved Note: bits 1 and 0 must be clear on systems not supporting ECC SeeAlso: #01155,#01157,#01142,#01129 Bitfields for Intel 82443BX Error Status Register: Bit(s) Description (Table 01157) 15-13 reserved (0) 12 (write-clear) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Read thermal throttling condition occurred 11 (write-clear) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Write thermal throttling condition occurred 10 (write-clear) AGP non-snoopable access outside Graphics Aperture 9 (write-clear) invalid AGP non-snoopable DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. read access 8 (write-clear) invalid Graphics Aperture Translation Table entry 7-5 (read-only) number of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row containing first multi-bit error 4 (write-clear) multi-bit (uncorrectable) error occurred 3-1 (read-only) number of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row containing first single-bit error 0 (write-clear) single-bit (correctable) error occurred SeeAlso: #01156,#01142 Bitfields for Intel AGP Capability Identifier: Bit(s) Description (Table 01158) 31-24 reserved 23-20 major version of supported AGP revision 19-16 minor version of supported AGP revision 15-8 offset of next capability (0 = none) 7-0 PCI capability ID (2 = AGP, 0 = disabled) SeeAlso: #01142,#01159,#01129 Bitfields for Intel 82443BX/EX/LX AGP Status Register: Bit(s) Description (Table 01159) 31-24 maximum AGP request queue depth (read-only) 23-10 reserved 9 AGP side band addressing is supported (read-only) 8-2 reserved 1-0 supported AGP data transfer type(s) bit 0: 1x data transfer mode bit 1: 2x data transfer mode Note: bits 0 and 1 may not both be clear SeeAlso: #01160,#01142,#01158,#01129 Bitfields for Intel 82443BX/EX/LX AGP Command Register: Bit(s) Description (Table 01160) 31-10 reserved 9 enable AGP sideband addressing 8 enable AGP 7-2 reserved 1-0 selected AGP transfer rate 00 = default 01 = 1x 10 = 2x 11 illegal SeeAlso: #01159,#01142,#01161,#01129 Bitfields for Intel 82443BX/EX/LX AGP Control Register: Bit(s) Description (Table 01161) 31-16 reserved (0) 15 disable forced ordering of snoopable writes and AGP reads (82443BX) (82443EX/LX) reserved 14 reserved (0) 13 enable Graphics Aperture Write-AGP Read synchronization 12-10 reserved (0) 9-8 reserved (0) (82443BX) expedite transaction throttle timer (82443EX/LX) 00 no throttling 01 reserved 10 192 clocks on, 64 clocks off 11 reserved 7 enable Graphics Translation Lookaside Buffer (and GTLB FlushTo force the copying of any data still stored in temporary buffers to its final destination. Control) 6-0 reserved (0) SeeAlso: #01160,#01142,#01129 Bitfields for Intel 82443BX/EX/LX Graphics Aperture Size Control: Bit(s) Description (Table 01162) 7-6 reserved 5-0 aperture size 000000 256M 100000 128M 110000 64M 111000 32M 111100 16M 111110 8M 111111 4M other illegal SeeAlso: #01142,#01163,#01129 Bitfields for Intel 82443BX/EX/LX Graphics Aperture Trans. Table Base Register: Bit(s) Description (Table 01163) 31-12 bits 31-12 of aperture translation table base address 11-0 reserved (0) SeeAlso: #01162,#01142,#01129 Bitfields for Intel 82443BX Memory Buffer Frequency Select: Bit(s) Description (Table 01164) 23 reserved 22 MAA[13:0], WEA#, SRASA#, SCASA# buffer select =0 66 MHz buffers =1 100 MHz buffers 21 MAB[12:11,9:0]#, MAB[13,10], WEB#, SRASB#, SCASB# buffer select (as for bit 22) 20 MD[63:0] (control 2) buffer select 19 MD[63:0] (control 1) buffer select 18 MECC[7:0] (control 2) buffer select 17 MECC[7:0] (control 1) buffer select 16 CSB7#/CKE5 buffer select 15 CSA7#/CKE3 buffer select 14 CSB6#/CKE4 buffer select 13 CSA6#/CKE2 buffer select 12 CSA5#/RASA5#, CSB5#/RASB5# buffer select 11 CSA4#/RASA4#, CSB4#/RASB4# buffer select 10 CSA3#/RASA3#, CSB3#/RASB3# buffer select 9 CSA2#/RASA2#, CSB2#/RASB2# buffer select 8 CAS1#/RASA1#, CSB1#/RASB1# buffer select 7 CSA0#/RASA0#, CSB0#/RASB0# buffer select 6 DQMA5/CASA5# buffer select 5 DQMA1/CASA1# buffer select 4 DQMB5/CASB5# buffer select 3 DQMB1/CASB1# buffer select 2 DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# buffer select 1 CKE1/GCKE buffer select 0 CKE0/FENA buffer select SeeAlso: #01142,#01166 Bitfields for Intel 82443BX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Read/Write Thermal Throttling Control: Bit(s) Description (Table 01165) 63 lock all read and write throttle control register bits (exists in Write Throttling control register only) 62-46 reserved 45-38 global DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. sampling window (in four-millisecond units) 37-26 global QWORD(quad-word) Eight bytes. See also DWORD, PWORD. threshold (documented as units of 215, but may be typo and actually be units of 2^15 = 32768) thermal throttling will be invoked if the number of QWORD(quad-word) Eight bytes. See also DWORD, PWORD. accesses during the sampling window exceeds the threshold count 25-20 throttle time in multiples of the sampling window 19-13 throttle monitoring window in 16 DRAM-clock units 12-3 throttle QWORD(quad-word) Eight bytes. See also DWORD, PWORD. maximum count -- while throttling is enabled, at most this many QWORD(quad-word) Eight bytes. See also DWORD, PWORD. accesses are permitted during each throttle monitoring window 2-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Throttle Mode 100 normal operation else Intel Reserved SeeAlso: #01142 Bitfields for Intel 82443BX Buffer Control Register: Bit(s) Description (Table 01166) 15-10 reserved 9-6 AGP Jam Latch strength bit 9: enable strong pull-up bit 8: enable weak pull-up bit 7: enable strong pull-down bit 6: enable weak pull-down 5-0 Intel Reserved SeeAlso: #01142,#01164 Format of PCI Configuration for Intel 82371FB/82371SB Function 0 (ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Bridge): Offset Size Description (Table 01167) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 122Eh/7000h) (revision ID 00h = 82371SB step A-1) (revision ID 01h = 82371SB step B-0) 40h 12 BYTEs reserved 4Ch BYTE ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. I/O Controller Recovery Timer (see #01087) 4Dh BYTE reserved 4Eh BYTE X-Bus Chip Select Enable (see #01089) 4Fh BYTE (82371SB) X-Bus Chip Select Enable High (see #01102) bit 0: I/O APIC enabled 4Fh BYTE (82371FB) reserved 50h 16 BYTEs reserved 60h 4 BYTEs PCI IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Route Control (see #01076) 64h 5 BYTEs reserved 69h BYTE top of memory (see #01216) 6Ah WORD miscellaneous status (see #01217) 6Ch 4 BYTEs reserved 70h BYTE motherboard IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Route Control 0 (see #01218) 71h BYTE (82371FB) motherboard IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Route Control 1 (see #01218) 72h 4 BYTEs reserved 76h 2 BYTEs motherboard DMAsee Direct Memory Access control (see #01219) 78h WORD programmable chip select control (see #01220) 7Ah 6 BYTEs reserved 80h BYTE (82371SB) APIC Base Address Relocation (see #01078) 81h BYTE reserved 82h BYTE (82371SB) Deterministic Latency Control (see #01221) 83h 29 BYTEs reserved A0h BYTE SMI Control (see #01222) A1h BYTE reserved A2h WORD SMI Enable (see #01080) A4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. System Event Enable (SEE) (see #01081) A8h BYTE Fast-Off Timer (in minutes, PCICLKs, or milliseconds) value is count less one; timer must be stopped before changing its value A9h BYTE reserved AAh WORD SMI Request (see #01082) ACh BYTE Clock Scale STPCLK# Low Timer STPCLK# stays low for 1+1056*(value+1) PCICLKs ADh BYTE reserved AEh BYTE Clock Scale STPCLK# High Timer STPCLK# stays high for 1+1056*(value+1) PCICLKs AFh 81 BYTEs reserved SeeAlso: #00873,#01214,#01215,#01064,#01083,#01108,#01098 Format of PCI configuration for Intel 82371MX MPIIX: Offset Size Description (Table 01168) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 1234h) 40h 9 BYTEs reserved 49h BYTE serial and parallel port enable (see #01169) 4Ah 2 BYTEs reserved 4Ch BYTE Extended I/O Controller Recovery Timer (see #01170) 4Dh BYTE reserved 4Eh BYTE BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. enable (see #01171) 4Fh BYTE FDC enable (see #01172) 50h 16 BYTEs reserved 60h BYTE PIRQA# Route Control (see #01076) 61h BYTE PIRQB# Route Control (see #01076) 62h 8 BYTEs reserved 6Ah WORD Miscellaneous Status (see #01173) 6Ch WORD IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing modes (see #01223) 6Eh 2 BYTEs reserved 70h BYTE Motherboard IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Route Control (see #01223) 71h 5 BYTEs reserved 76h 3 BYTEs Motherboard DMAsee Direct Memory Access Route Control (see #01219) 79h 5 BYTEs reserved 7Eh BYTE Audio enable (see #01174) 7Fh BYTE DMAsee Direct Memory Access channel 5-7 address size (see #01175) 80h BYTE PCI DMAsee Direct Memory Access enable (see #01176) 81h 7 BYTEs reserved 88h BYTE PCI DMAsee Direct Memory Access/PCI DMAsee Direct Memory Access expansion A (see #01177) 89h BYTE PCI DMAsee Direct Memory Access/PCI DMAsee Direct Memory Access expansion B (see #01177) 8Ah WORD Programmable Memory Address Control 0 (see #01178) 8Ch WORD Programmable Memory Address Control 1 (see #01178) 8Eh WORD Programmable Memory Address Mask (see #01179) 90h BYTE Programmable Address Range Enable (see #01180) 91h BYTE reserved 92h WORD Programmable Chip Select Control (see #01181) 94h WORD Programmable Address Control 1 (see #01182) 96h WORD Programmable Address Control 2 (see #01182) 98h WORD Programmable Address Control 3 (see #01182) 9Ah BYTE Programmable Address Mask A (see #01183) 9Bh BYTE Programmable Address Mask B (see #01184) 9Ch WORD I/O configuration address (see #01185) 9Eh 2 BYTEs reserved A0h WORD Programmable Address Control 4 (see #01182) A2h WORD Programmable Address Control 5 (see #01182) A4h BYTE Programmable Address Mask C (see #01186) A5h BYTE Peripheral Access Detect Enable 0 (see #01187) A6h BYTE Peripheral Access Detect Enable 1 (see #01188) A7h BYTE Peripheral Access Detect Enable 2 (see #01189) A8h WORD Local Trap Address for Device 3 (see #01190) AAh BYTE Local Trap Mask for Device 3 (see #01191) ABh BYTE Local Trap SMI Enable (see #01192) ACh 2 BYTEs reserved AEh BYTE Local Trap SMI Status (see #01192) AFh BYTE reserved B0h BYTE Local Standby SMI Enable (see #01193) B1h BYTE Local Standby Timer Reload Enable (see #01194) B2h BYTE Local Standby SMI Status (see #01193) B3h BYTE reserved B4h BYTE Local Standby Timer IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. Idle (see #01195) B5h BYTE Local Standby Timer Audio Idle (see #01195) B6h BYTE Local Standby Timer COM Idle (see #01195) B7h BYTE reserved B8h BYTE Local Standby Timer Device 1 Idle (see #01195) B9h BYTE Local Standby Timer Device 2 Idle (see #01195) BAh BYTE Local Standby Timer Device 3 Idle (see #01195) BBh BYTE reserved BCh BYTE Software/EXTSMI# SMI Delay Timer (see #01195) BDh BYTE Suspend SMI Delay Timer (see #01195) BEh BYTE Global Standby Timer (see #01195) BFh BYTE Clock Throttle Standby Timer (see #01195) C0h BYTE System Management Control (see #01196) C1h BYTE System SMI Enable (see #01197) C2h BYTE Miscellaneous SMI Enable (see #01198) C3h BYTE Global SMI Enable (see #01200) C4h 2 BYTEs reserved C6h BYTE System SMI Status (see #01197) C7h BYTE Miscellaneous SMI Status (see #01199) C8h BYTE Global SMI Status (see #01201) C9h 3 BYTEs reserved CCh BYTE Suspend/Resume Control 1 (see #01202) CDh BYTE Suspend/Resume Control 2 (see #01203) CEh BYTE SMOUT Control (see #01204) CFh BYTE reserved D0h BYTE System Event Enable 0 (see #01207) D1h BYTE System Event Enable 1 (see #01208) D2h BYTE System Event Enable 2 (see #01209) D3h BYTE Burst Count Timer (see #01195) D4h BYTE Clock Control (see #01205) D5h BYTE reserved D6h BYTE STPCLK# Low Timer (see #01195) D7h BYTE STPCLK# High Timer (see #01195) D8h BYTE Stop Break Event Enable 0 (see #01207) D9h BYTE Stop Break Event Enable 1 (see #01208) DAh BYTE Stop Break Event Enable 2 (see #01209) DBh 5 BYTEs reserved E0h BYTE Shadow Register (see #01206) E1h 3 BYTEs reserved E4h BYTE Burst Clock Event Enable 0 (see #01207) E5h BYTE Burst Clock Event Enable 1 (see #01208) E6h BYTE Burst Clock Event Enable 2 (see #01209) E7h BYTE Burst Clock Event Enable 3 (see #01210) E8h BYTE Burst Clock Event Enable 4 (see #01211) E9h BYTE Burst Clock Event Enable 5 (see #01212) EAh BYTE Burst Clock Event Enable 6 (see #01213) EBh BYTE reserved ECH BYTE Clock Throttle Break Event Enable 0 (see #01207) EDh BYTE Clock Throttle Break Event Enable 1 (see #01208) EEh BYTE Clock Throttle Break Event Enable 2 (see #01209) EFh BYTE Clock Throttle Break Event Enable 3 (see #01210) F0h BYTE Clock Throttle Break Event Enable 4 (see #01211) F1h BYTE Clock Throttle Break Event Enable 5 (see #01212) F2h BYTE Clock Throttle Break Event Enable 6 (see #01213) F3h 13 BYTES reserved SeeAlso: #00873,#01076 Bitfields for Intel 82371MX serial and parallel port enable register: Bit(s) Description (Table 01169) 7 reserved 6 LPT3 enabled 5 LPT2 enabled 4 LPT1 enabled 3 COM4 enabled 2 COM3 enabled 1 COM2 enabled 0 COM1 enabled SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Extended I/O Controller Recovery Timer register: Bit(s) Description (Table 01170) 7 reserved 6 8-Bit I/O Recovery Enable =1 Enable value programmed into bits 5-3 5-3 8-Bit I/O Recovery Times 000 = 8 SYSCLK 001 = 1 SYSCLK (default) 010 = 2 SYSCLK 011 = 3 SYSCLK 100 = 4 SYSCLK 101 = 5 SYSCLK 110 = 6 SYSCLK 111 = 7 SYSCLK 2-0 Reserved (0) SeeAlso: #01168,#01087,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. enable register: Bit(s) Description (Table 01171) 7 Extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Enable 6 Lower BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Enable 1 5 Lower BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Enable 0 4 Lower BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. CS# Enable 0 3 F Segment BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Enable 2 BIOSCS# Write Protect 1-0 reserved SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX FDC Enable register: Bit(s) Description (Table 01172) 7 Coprocessor Error fuction Enable 6 IRQ12/M Mouse Function Enable 5 System Management Output 5/Disk Output Enable 4 System Management Output 4/RTCALE Enable 3 Motherboad DMAsee Direct Memory Access 2 Disable 2 reserved 1 Floppy Secondary Addess Enable 0 Floppy Primary Address Enable SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Miscellaneous Status register: Bit(s) Description (Table 01173) 15-3 reserved 2-1 reserved (0) 0 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Clock Divisor Status =1 Divisor=3 (PCICLK=25MHz) default =0 Divisor=4 (PCICLK=33MHz) Note: This is a read-only register that reports on chipset jumper settings. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Audio enable register: Bit(s) Description (Table 01174) 7 Audio enabled 6-4 Reserved 3-2 Audio I/O Address 00 0220h 01 0230h 10 0240h 11 0250h 1-0 reserved SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX DMAsee Direct Memory Access channel 5-7 address size register: Bit(s) Description (Table 01175) 7 Channel 7 16/8-Bit Count by Word/Byte =1 16-bit, count by word =0 8-bit, count by byte 6 Channel 6 16/8-Bit Count by Word/Byte (same values as bit 7) 5 Channel 5 16/8-Bit Count by Word/Byte (same values as bit 7) 4-3 reserved (0) SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX PCI DMAsee Direct Memory Access Enable register: Bit(s) Description (Table 01176) 7 DMAsee Direct Memory Access CH7 is on PCI Bus 6 DMAsee Direct Memory Access CH6 is on PCI Bus 5 DMAsee Direct Memory Access CH5 is on PCI Bus 4 reserved 3 DMAsee Direct Memory Access CH3 is on PCI Bus 2 DMAsee Direct Memory Access CH2 is on PCI Bus 1 DMAsee Direct Memory Access CH1 is on PCI Bus 0 DMAsee Direct Memory Access CH0 is on PCI Bus SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX PCI DMAsee Direct Memory Access/PCI DMAsee Direct Memory Access expansion registers: Bit(s) Description (Table 01177) 7-4 reserved 3 Expansion enabled 2-0 DMAsee Direct Memory Access channel Note: The PCI DMAsee Direct Memory Access Expansion request lines (REQ[A,B]#/GNT[A,B]#) provide PCI DMAsee Direct Memory Access and PCI DMAsee Direct Memory Access expansion support. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Memory Address Control registers: Bit(s) Description (Table 01178) 15-0 Memory Access Control SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Memory Address Mask register: Bit(s) Description (Table 01179) 7-0 Memory Address Mask SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Address Range Enable register: Bit(s) Description (Table 01180) 7 PCS# Enabled for Programmable Address Range 2 6 PCS# Enabled for Programmable Address Range 1 5 Programmable Address range 5 Enabled 4 Programmable Address range 4 Enabled 3 Programmable Address range 5 Enabled 2 Programmable Address range 3 Enabled 1 Programmable Address range 1 Enabled 5 PCS# Address range Enabled SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Chip Select Control register: Bit(s) Description (Table 01181) 15-0 PCS# Address SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Address Control registers: Bit(s) Description (Table 01182) 15-0 Programmable Address Control Note: This register selects a 16-bit I/O address range to be forwarded to the Extended I/O Bus, if enabled in the Programmable Address Range register. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Address Mask A register: Bit(s) Description (Table 01183) 7-4 Programmable Address Control 1 Mask 3-0 Programmable Chip Select Mask SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Address Mask B register: Bit(s) Description (Table 01184) 7-4 Programmable Address Control 3 Mask 3-0 Programmable Address Control 2 Mask SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX I/O configuration address register: Bit(s) Description (Table 01185) 15-10 reserved 9-1 I/O Configuration Address 0 I/O Configuration Address Enabled Note: This register provides an I/O address range to be forwarded to the Extended I/O Bus for accesses to the configuration space of an integrated I/O device. PCI address bits 9-1 are compared to bits 9-1 of this register. Address bits 31-10 must be 0. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Programmable Address Mask C register: Bit(s) Description (Table 01186) 7-4 Programmable Address Control 5 Mask 3-0 Programmable Address Control 4 Mask SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Peripheral Access Detect Enable 0 register: Bit(s) Description (Table 01187) 7 Enable Audio-E 6 Enable Audio-D 5 Enable Audio-C 4 Enable Audio-B 3 Enable Audio-A 2 Enable Parallel 3 1 Enable Parallel 2 0 Enable Parallel 1 SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Peripheral Access Detect Enable 1 register: Bit(s) Description (Table 01188) 7 Enable COM4 6 Enable COM3 5 Enable COM3 4 Enable COM1 3 Enable Secondary FDC 2 Enable Primary FDC 1 Enable Secondary IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. 0 Enable Promary IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Peripheral Access Detect Enable 2 register: Bit(s) Description (Table 01189) 7 Enable PMAC1 6 Enable PMAC0 5 Enable PAC5 4 Enable PAC4 3 Enable PAC3 2 Enable PAC2 1 Enable PAC1 0 Enable PCSC SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Local Trap Address for Device 3 register: Bit(s) Description (Table 01190) 15-0 Local Trap Address base for Device 3 Note: Is compared with bits 15-0 of PCI I/O Addresses. Address bits 31-16 must be 0. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Local Trap Mask for Device 3 register: Bit(s) Description (Table 01191) 7-4 Local Trap COM Port Select =1000 COM4 02E8h-02EFh =0100 COM3 03E8h-83EFh =0010 COM2 02F8h-02FFh =0001 COM1 03F8h-03FFh Note: These bits when set cause an SMI# when access to the corresponding I/O port range is made. 3-0 Local Trap Mask Note: This field selects the range of trappable addresses (in bytes). SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Local Trap SMI Enable/Status registers: Bit(s) Description (Table 01192) 7-6 reserved 5 IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. 4 Audio 3 COM 2 DEV3 1 DEV2 0 DEV1 Note: a set bit indicates in the Enable register turns generation of SMI# on I/O accesses to the address region used by the selected device; a set bit in the Status register indicates which trap caused an SMI# interrupt. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Local Standby SMI Enable/Status registers: Bit(s) Description (Table 01193) 7-6 reserved 5 IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. 4 Audio 3 COM 2 DEV3 1 DEV2 0 DEV1 Note: each bit in the Enable register turns on the associated SMI Timer; a set bit in the Status register indicates which local standby timer caused the SMI interrupt SeeAlso: #01168,#01194,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Local Standby Timer Reload Enable register: Bit(s) Description (Table 01194) 7 IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. 6 Audio 5 COM 4 DEV3 3 DEV2 2 DEV1 1 Audio MDAK2 0 Audio MDAK1 Note: This register enables local standby timer reloading. When the associated I/O address range is accessed, the standby timer is reloaded with it's default value. Also note the different bit-order for this register only. SeeAlso: #01168,#01193,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Count Value registers: Bit(s) Description (Table 01195) 7-0 Count value Note: This field contains the initial count value for various time-out events. 00 is an illegal programmed value. The programmed value is decremented by certain events or system clocks, and the event is triggered when the count reaches 0. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX System Management Control register: Bit(s) Description (Table 01196) 7-3 reserved 2 Freeze (but not reset) all Power Management timers 1 =0 disable all Power Management functions 0 =0 disable SMI SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX System SMI Enable/Status registers: Bit(s) Description (Table 01197) 7 reserved 6 Write to APMC Port (software SMI) 5 EXTSMI# 4 IRQ12 3 IRQ8 2 IRQ4 1 IRQ3 0 IRQ1 Note: each set bit in the Enable register turns on SMI# generation for the associated hardware event; a set bit in the Status register indicates which event caused the SMI interrupt SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Miscellaneous SMI Enable register: Bit(s) Description (Table 01198) 7-4 reserved 3 Write to APMC Port 2 SRBTN# 1 BATLOW# 0 reserved Note: Enables SMI# generation for the above hardware events SeeAlso: #01168,#01199,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Miscellaneous SMI Status register: Bit(s) Description (Table 01199) 7-4 reserved 3 =1 indicates system is in global standby mode 2 SRBTN# caused SMI 1 BATLOW# caused SMI 0 reserved SeeAlso: #01168,#01198,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Global SMI Enable register: Bit(s) Description (Table 01200) 7 System Events Enabled 6 Software SMI#'s (generated by bit 0 of this register) Enabled 5 reserved 4 Local Traps Enabled 3 Local Standby Timers Enabled 2 Global Standby Timer Enabled 1 SRBTN# and BATLOW# Enabled Note: Enables SMI# generation for the above hardware events SeeAlso: #01168,#01201,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Global SMI Status register: Bit(s) Description (Table 01201) 7 One of the System Events caused SMI 6 Software SMI or EXTSMI# caused SMI 5 Write to APMC caused SMI 4 Access to one of the Local Traps caused SMI 3 One of the local Standby timers caused SMI 2 Global Standby Timer caused SMI 1 SRBTN# or BATLOW# caused SMI 0 reserved SeeAlso: #01168,#01200,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Suspend/Resume Control 1 register: Bit(s) Description (Table 01202) 7 BATLOW# bypasses Suspend delay timer and activates SMI# immediately 6 IRQ8 will NOT cause a resume 5 COM RI (Ring) will NOT cause a resume ("Wake on Ring" function) 4 BATLOW# will not prevent a resume 3 is set by power management software at the end of a suspend routine 2 can be set by power management software at the end of a suspend routine 1-0 Set suspend mode 00 Suspend Disabled 01 reserved 10 Suspend-to-DRAM 11 Suspend-to-Disk SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Suspend/Resume Control 2 register: Bit(s) Description (Table 01203) 7-1 reserved 0 EXTSMI# will NOT cause a resume event SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX SMOUT Control register: Bit(s) Description (Table 01204) 7-6 reserved 5-0 Writing to any bits sets the state of the 6 SMOUTx pins. SMOUT5 is not effected if it is configured for DOE# function SMOUT4 is not effected if it is configured for RTCALE function SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Clock Control register: Bit(s) Description (Table 01205) 7 Clock Throttle standy by timer frequency =1 32ms =0 4ms Note: Sets the granularity of the Clock Throttle Standby Timer 6-5 reserved 4 Enable Auto Clock Throttle 3-2 STPCLK# Mode 00 Disable STPCLK# Function 01 Enable stop grant mode 10 Enable stop clock mode 11 reserved 1 Enable clock throttling 0 Enable "PCI Clock can be stopped" SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" (Table 01206) Values for Intel 82371MX Shadow Register Value ATIBM PC AT Port Description 00h 00h Channel 0 Base Address Register (low byte) 01h 00h Channel 0 Base Address Register (high byte) 02h 01h Channel 0 Base Word Count Register (low byte) 03h 01h Channel 0 Base Word Count Register (high byte) 04h 02h Channel 1 Base Address Register (low byte) 05h 02h Channel 1 Base Address Register (high byte) 06h 03h Channel 1 Base Word Count Register (low byte) 07h 03h Channel 1 Base Word Count Register (high byte) 08h 04h Channel 2 Base Address Register (low byte) 09h 04h Channel 2 Base Address Register (high byte) 0Ah 05h Channel 2 Base Word Count Register (low byte) 0Bh 05h Channel 2 Base Word Count Register (high byte) 0Ch 06h Channel 3 Base Address Register (low byte) 0Dh 06h Channel 3 Base Address Register (high byte) 0Eh 07h Channel 3 Base Word Count Register (low byte) 0Fh 07h Channel 3 Base Word Count Register (high byte) 10h 08h DMA1 Command Register 11h 0Bh Channel 0 Mode Register 12h 0Bh Channel 1 Mode Register 13h 0Bh Channel 2 Mode Register 14h 0Bh Channel 3 Mode Register 15h 0Fh DMA1 Mask Register 16h C4h Channel 5 Base Address Register (low byte) 17h C4h Channel 5 Base Address Register (high byte) 18h C6h Channel 5 Base Word Count Register (low byte) 19h C6h Channel 5 Base Word Count Register (high byte) 1Ah C8h Channel 6 Base Address Register (low byte) 1Bh C8h Channel 6 Base Address Register (high byte) 1Ch CAh Channel 6 Base Word Count Register (low byte) 1Dh CAh Channel 6 Base Word Count Register (high byte) 1Eh CCh Channel 7 Base Address Register (low byte) 1Fh CCh Channel 7 Base Address Register (high byte) 20h CDh Channel 7 Base Word Count Register (low byte) 21h CDh Channel 7 Base Word Count Register (high byte) 22h D0h DMA2 Command Register 23h D6h Channel 5 Mode Register 24h D6h Channel 6 Mode Register 25h D6h Channel 7 Mode Register 26h DEh DMA2 Mask Register 27h 20h PIC1 ICW1 28h 21h PIC1 ICW2 29h 21h PIC1 ICW3 2Ah 21h PIC1 ICW4 2Bh 20h PIC1 OCW2 2Ch A0h PIC2 ICW1 2Dh A1h PIC2 ICW2 2Eh A1h PIC2 ICW3 2Fh A1h PIC2 ICW4 30h A0h PIC2 OCW2 31h 70h NMIsee Non-Maskable Interrupt mask / RTCsee Real-Time Clock address 32h 03FAh COM1 FIFO Enable Register (only bits 0,3,6 & 7 valid) 33h 02FAh COM2 FIFO Enable Register (only bits 0,3,6 & 7 valid) 34h 03EAh COM3 FIFO Enable Register (only bits 0,3,6 & 7 valid) 35h 02EAh COM4 FIFO Enable Register (only bits 0,3,6 & 7 valid) 36h 40h TIMER 0 Count Register (low byte) 37h 40h TIMER 0 Count Register (high byte) 38h 20h Master PIC OCW3 Register (bits 0,2 & 5 only valid) 39h A0h Slave PIC OCW3 Register (bits 0,2 & 5 only valid) Desc: This register is used to read the current programmed value of certain ATIBM PC AT compatable I/O ports which are traditionally write-only. Note: To read a given register, write the value from the table to the shadow register, then immediately re-read the shadow register. The returned value is the current value of the I/O port. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Burst Clock/Clock Throttle Break Enable 0 register: Bit(s) Description (Table 01207) 7 Enable IRQ7 6 Enable IRQ6 5 Enable IRQ7 4 Enable IRQ4 3 Enable IRQ3 2 reserved 1 Enable IRQ1 0 Enable IRQ0 SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Event Enable 1 register: Bit(s) Description (Table 01208) 7 Enable IRQ15 6 Enable IRQ14 5 reserved 4 Enable IRQ12 3 Enable IRQ11 2 Enable IRQ10 1 Enable IRQ9 0 Enable IRQ8 SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Event Enable 2 register: Bit(s) Description (Table 01209) 7 (Clock Throttle Break Event,Burst Clock Event) reserved (System Event,Stop Break Event,Clock Throttle Break Event) Enable BATLOW# & SRBTN# 6 Enable EXTSMI# 5 Enable SMI# 4 (System Event,Stop Break Event,Clock Throttle Break Event) Enable NMIsee Non-Maskable Interrupt (Burst Clock Event) reserved 3 (System Event,Stop Break Event,Clock Throttle Break Event) Enable INTR (Burst Clock Event) reserved 2 reserved 1 Enable COMRI# 0 Enable events of selected type SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Event Enable 3 register: Bit(s) Description (Table 01210) 7-2 reserved 1 Enable EXTEVNT# 0 Enable PHLDA# SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Event Enable 4 register: Bit(s) Description (Table 01211) 7 Enable PMAC1 6 Enable PMAC0 5 Enable PAC5 4 Enable PAC4 3 Enable PAC3 2 Enable PAC2 1 Enable PAC1 0 Enable PCSC SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Event Enable 5 register: Bit(s) Description (Table 01212) 7 Enable COM4 6 Enable COM3 5 Enable COM3 4 Enable COM1 3 Enable Secondary FDC 2 Enable Primary FDC 1 Enable Secondary IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. 0 Enable Promary IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Bitfields for Intel 82371MX Event Enable 6 register: Bit(s) Description (Table 01213) 7 Enable Audio-E 6 Enable Audio-D 5 Enable Audio-C 4 Enable Audio-B 3 Enable Audio-A 2 Enable Parallel 3 1 Enable Parallel 2 0 Enable Parallel 1 SeeAlso: #01168,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371" Format of PCI Configuration for Intel 82371FB/82371SB Function 1 (IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI.): Offset Size Description (Table 01214) 00h 64 BYTEs header (see #00878) (vender ID 8086h, device ID 1230h/7010h) 20h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Bus Master Interface Base Address (see PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371SB") 40h WORD IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing modes, primary channel (see #01223) 42h WORD IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing modes, secondary channel (see #01223) 44h BYTE (82371SB) slave IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing register (see #01224) 45h 187 BYTEs reserved SeeAlso: #01167,#01215,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371SB" Format of PCI Configuration data for Intel 82371SB Function 2 (USBsee Universal Serial Bus): Offset Size Description (Table 01215) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 7020h) 20h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O space base address (see PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371SB") 40h 32 BYTEs reserved 60h BYTE Serial Bus Specification release number 00h pre-release 1.0 10h Release 1.0 61h 9 BYTEs reserved 6Ah WORD miscellaneous status (see #01225) 6Ch 84 BYTEs reserved C0h WORD legacy support (see #01226) C2h 62 BYTEs reserved SeeAlso: #01167,#01214,PORTIBM PC Portable (uses same BIOS as XT) xxxxh"Intel 82371SB" Bitfields for Intel 82371FB/82371SB top of memory register: Bit(s) Description (Table 01216) 7-4 top of ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. memory (in megabytes, less 1; i.e. 0001 = 2M) 3 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA./DMAsee Direct Memory Access lower BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. forwarding enable 2 (82371SB) enable A000/B000 segment forwarding to PCI bus 1 enable forwarding ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA./DMAsee Direct Memory Access 512K-640K region to PCI bus 0 reserved SeeAlso: #01167,#01217 Bitfields for Intel 82371FB/82371SB miscellaneous status register: Bit(s) Description (Table 01217) 15 (82371SB) enable SERR# on delayed transaction write 1 to clear this bit 14-8 reserved 7 (82371SB) NB Retry Enable 6 (82371SB) EXTSMI# Mode Enable allow special SERR# protocol between PCI bridge and 82371 5 reserved 4 (82371SB) enable USBsee Universal Serial Bus disable USBsee Universal Serial Bus's master enable and I/O decode enable prior to clearing this bit! 3 reserved 2 (82371FB) PCI Header Type Bit enable =1 report multifunction device in PCI configuration header 1 (82371FB) internal ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. DMAsee Direct Memory Access/external DMAsee Direct Memory Access Mode status (read-only) =0 normal DMAsee Direct Memory Access operation 0 (82371FB) ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Clock Divisor status (read-only) (82371SB) ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. Clock Divisor (read-write) =1 SYSCLK clock divisor is 3 =0 SYSCLK clock divisor is 4 SeeAlso: #01167,#01216 Bitfields for Intel 82371FB/82371SB/82371MX motherboard IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Route Control: Bit(s) Description (Table 01218) 7 disable IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. routing 6 enable MIRQx/IRQx sharing 5 (82371SB only) enable IRQ0 output 4 reserved (0) 3-0 ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA. IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. number to which to route the PCI IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. Notes: IRQs 0-2, 8, and 13 are reserved interrupt sharing should only be enabled when the device connected to the MIRQ line and the device connected to the IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. line both produce active high, level triggered interrupts. SeeAlso: #01167,#01168,#01216,#01219 Bitfields for Intel 82371FB/82371SB/82371MX motherboard DMAsee Direct Memory Access control: Bit(s) Description (Table 01219) 7 type F DMAsee Direct Memory Access buffer enable 6-4 reserved 3 (82371FB only) disable motherboadr DMAsee Direct Memory Access channel (SB/MX) reserved (0) 2-0 DMAsee Direct Memory Access channel number (100 = disabled [default]) (82371FB) Type F and Motherboard DMAsee Direct Memory Access (82371SB/MX) Type F DMAsee Direct Memory Access SeeAlso: #01167,#01168,#01218 Bitfields for Intel 82371FB/83271SB programmable chip select control register: Bit(s) Description (Table 01220) 15-2 I/O address which will assert PCS# signal 1-0 PCS address mask 00 four bytes 01 eight contiguous bytes 10 disabled 11 sixteen contiguous bytes SeeAlso: #01167,#01219,#01221 Bitfields for Intel 82371SB Deterministic Latency Control register: Bit(s) Description (Table 01221) 7-4 reserved 3 enable SERR# on delayed transaction timeout 2 enable USBsee Universal Serial Bus passive release 1 enable passive release 0 enable delayed transactions SeeAlso: #01167,#01220 Bitfields for Intel 82371FB/82371SB SMI Control Register: Bit(s) Description (Table 01222) 7-5 reserved 4-3 Fast-Off Timer freeze/granularity selection 00 one minute granularity (assuming 33 MHz PCICLK) 01 disabled (frozen) 10 one PCICLK 11 one millisecond 2 STPCLK# scaling enable =1 enable Clock Scale bytes in PCI configuration space 1 STPCLK# signal enable =1 assert STPCLK# on read from PORTIBM PC Portable (uses same BIOS as XT) 00B2h 0 SMI# Gate =1 enable SMI# on system management interrupt Notes: bit 1 is cleared either with an explicit write of 0 here, or by any write to PORTIBM PC Portable (uses same BIOS as XT) 00B2h bit 0 does not affect the recording of SMI events, so a pending SMI will cause an immediate SMI# when the bit is set SeeAlso: #01167,#01079 Bitfields for Intel 82371FB/82371SB/82371MX IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing modes: Bit(s) Description (Table 01223) 15 IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. decode enable 14 (82371SB) slave IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing register enable (see #01224) (82371MX) primary/secondary address decode (=0 primary, =1 secondary) 13-12 IORDY# sample point 00 five clocks after DIOx# assertion 01 four clocks 10 three clocks 11 two clocks 11-10 reserved 9-8 recovery time between IORDY# sample point and DIOx# 00 four clocks 01 three clocks 10 two clocks 11 one clock 7 (FB/SB) DMAsee Direct Memory Access timing enable only, drive 1 (MX) reserved 6 prefetch and posting enable, drive 1 5 IORDY# sample point enable drive select 1 4 fast timing bank drive select 1 3 (FB/SB) DMAsee Direct Memory Access timing enable only, drive 0 (MX) reserved 2 prefetch and posting enable, drive 0 1 IORDY# sample point enable drive select 0 0 fast timing bank drive select 0 SeeAlso: #01214,#01168 Bitfields for Intel 82371SB slave IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. timing register: Bit(s) Description (Table 01224) 7-6 secondary drive 1 IORDY# sample point 00 five clocks after DIOx# assertion 01 four clocks 10 three clocks 11 two clocks 5-4 secondary drive 1 recovery time 00 four clocks 01 three clocks 10 two clocks 11 one clock 3-2 primary drive 1 IORDY# sample point 1-0 primary drive 1 recovery time SeeAlso: #01223 Bitfields for Intel 82371SB miscellaneous status: Bit(s) Description (Table 01225) 15-1 reserved 0 USBsee Universal Serial Bus clock selection =1 48 MHz =0 24 MHz SeeAlso: #01215,#01226 Bitfields for Intel 82371SB legacy support register: Bit(s) Description (Table 01226) 15 A20GATE pass-through sequence ended write 1 to clear this bit 14 reserved 13 USBsee Universal Serial Bus PIRQ enabled 12 USR IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. status (read-only) 11 trap caused by write to PORTIBM PC Portable (uses same BIOS as XT) 0064h write 1 to clear this bit 10 trap caused by read from PORTIBM PC Portable (uses same BIOS as XT) 0064h write 1 to clear this bit 9 trap caused by write to PORTIBM PC Portable (uses same BIOS as XT) 0060h write 1 to clear this bit 8 trap caused by read from PORTIBM PC Portable (uses same BIOS as XT) 0060h write 1 to clear this bit 7 enable SMI at end of A20GATE Pass-Through 6 A20GATE pass-through sequence in progress (read-only) 5 enable A20GATE pass-through sequence (write PORTIBM PC Portable (uses same BIOS as XT) 64h,D1h; write 60h,xxh; read 64h; write 64h,FFh) 4 enable trap/SMI on USBsee Universal Serial Bus IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 3 enable trap/SMI on PORTIBM PC Portable (uses same BIOS as XT) 0064h write 2 enable trap/SMI on PORTIBM PC Portable (uses same BIOS as XT) 0064h read 1 enable trap/SMI on PORTIBM PC Portable (uses same BIOS as XT) 0060h write 0 enable trap/SMI on PORTIBM PC Portable (uses same BIOS as XT) 0060h read SeeAlso: #01215,#01225 Format of PCI Configuration Data for Intel 82557: Offset Size Description (Table 01227) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 1229h) (see #00873) 10h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. base address of memory-mapped Control/Status Registers (4K) (see #01228) 14h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. base address of I/O-mapped Control/Status Registers (32 ports) 18h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. base address of Flash memory (1M) 40h 192 BYTEs unused SeeAlso: #01098 Format of Intel 82557 Control/Status Registers: Offset Size Description (Table 01228) 00h WORD SCB status word 02h WORD SCB command word 04h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SCB general pointer 08h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. PORTIBM PC Portable (uses same BIOS as XT) 0Ch WORD Flash control register 0Eh WORD EEPROM control register 10h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. MDI control register 14h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. Early RCV Interrupt Rx byte count (RXBC) register Note: see http://www.intel.com/design/network/datashts/64434604.pdf for additional details SeeAlso: #01228 Format of PCI Configuration Data for Intel 82441FX: Offset Size Description (Table 01229) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 1237h) (see #00873) 40h 16 BYTEs reserved 50h WORD PMC Configuration (see #01230) 52h BYTE deturbo counter control when deturbo mode is selected (see PORTIBM PC Portable (uses same BIOS as XT) 0CF9h), the chipset places a hold on the memory bus for a fraction of the time inversely proportional to the value in this register (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.) 53h BYTE DBX buffer control (see #01231) 54h BYTE auxiliary control (see #01232) 55h WORD DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type (see #01233) 57h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control (see #01234) 58h BYTE DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing (see #01235) 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 8 BYTEs DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Buondary registers 0-7 each register N indicates cumulative amount of memory in rows 0-N (each 64 bits wide), in 8M units 68h BYTE Fixed DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Hole Control 69h 7 BYTEs reserved 70h BYTE Multi-Transaction Timer number of PCLKs guaranteed to the current agent before the 82441 will grant the bus to another PCI agent on request 71h BYTE CPU(Central Processing Unit) The microprocessor which executes programs on your computer. Latency Timer (see #01236) 72h BYTE System Management RAM(Random Access Memory) See also DRAM, SRAM. control (see #01123) 73h 29 BYTEs reserved 90h BYTE Error Command (see #01237) 91h BYTE Error Status (see #01238) 92h BYTE reserved 93h BYTE Turbo Reset Control (see #01239) 94h 108 BYTEs reserved SeeAlso: #01098,#01108 Bitfields for Intel 82441FX PMC Configuration Register: Bit(s) Description (Table 01230) 15 WSC Protocol Enable 14 Row Select/Extra Copy select (read-only) =1 pins on PMC configured as two additional row selects (6/7) =0 extra copy of two lowest memory address bits enabled 13-10 reserved 9-8 host frequence select 00 reserved 01 60 MHz 10 66 MHz 11 reserved 7 reserved 6 ECC/Parity TEST enable 5-4 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Data Integrity Mode 00 no parity/ECC 01 parity generated and checked 10 ECC generated and checked, correction disabled 10 ECC generated and checked, correction enabled 3 reserved 2 In-Order Queue size (0=one, 1=four) 1-0 reserved SeeAlso: #01229,#01231 Bitfields for Intel 82441FX DBX buffer control register: Bit(s) Description (Table 01231) 7 enable delayed transactions 6 enable CPU-to-PCI IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself. See also ESDI. posting 5 enable USWC Write Post during I/O Bridge access 4 disable PCI Delayed Transaction timer 3 enable CPU-to-PCI Write Post 2 enable PCI-to-DRAM pipeline 1 enable PCI Burst Write Combining 0 enable Read-Around-Write SeeAlso: #01229,#01230 Bitfields for Intel 82441FX auxiliary control register: Bit(s) Description (Table 01232) 7 enable RAS precharge 6-2 reserved 1 Lower Memory Address Buffer Set A =0 8mA =1 12mA 0 reserved SeeAlso: #01229 Bitfields for Intel 82441FX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Row Type register: Bit(s) Description (Table 01233) 15-14 row 7 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 13-12 row 6 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 11-10 row 5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 9-8 row 4 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 7-6 row 3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 5-4 row 2 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 3-2 row 1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 1-0 row 0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. type 00 fast page-mode DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 01 EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 10 BEDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. 11 empty row SeeAlso: #01229,#01234 Bitfields for Intel 82441FX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Control register: Bit(s) Description (Table 01234) 7 reserved 6 enable DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Queue 5 enable DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. EDO Auto-Detect Mode 4 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading. The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors. See also DRAM. Type =0 CASsee Communicating Applications Specification before RAS =1 RAS only 3 reserved 2-0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. refresh rate 000 disabled 001 normal (as set by PMCCFG register) 01x reserved 1xx reserved 111 fast refresh (every 32 host clocks) SeeAlso: #01229,#01233,#01235 Bitfields for Intel 82441FX DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Timing register: Bit(s) Description (Table 01235) 7 reserved 6 enable WCBR Mode 5-4 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Read Burst Timing BEDO EDO FPM 00 x333 x444 x444 01 x222 x333 x444 10 x222 x222 x333 11 res. res. res. 3-2 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. Write Burst Timing (B)EDO FPM 00 x444 x444 01 x333 x444 10 x333 x333 11 x222 x333 1 RAS-to-CAS delay =1 one clock =0 zero clocks 0 insert one MA Wait State SeeAlso: #01229,#01234 Bitfields for Intel 82441FX CPU(Central Processing Unit) The microprocessor which executes programs on your computer. Latency Timer register: Bit(s) Description (Table 01236) 7-5 reserved 4-0 snoop stall count value SeeAlso: #01229 Bitfields for Intel 82441FX Error Command register: Bit(s) Description (Table 01237) 7-5 reserved 4 enable SERR# on receiving Target Abort 3 enable SERR# on PCI Parity Error (PERR#) 2 reserved 1 enable SERR# on receiving multiple-bit ECC/Parity error 0 enable SERR# on receiving single-bit ECC error SeeAlso: #01229,#01238 Bitfields for Intel 82441FX Error Status register: Bit(s) Description (Table 01238) 7-5 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row causing first multi-bit error (read-only) 4 multiple-bit uncorrectable error detected write 1 to this bit to clear it 3-1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. row causing first single-bit error (read-only) 0 single-bit correctable ECC error detected write 1 to this bit to clear it SeeAlso: #01229,#01237 Bitfields for Intel 82441FX,82443EX/LX Turbo Reset Control register: Bit(s) Description (Table 01239) 7-4 reserved 3 enable BIST on hard reset 2 reset CPU(Central Processing Unit) The microprocessor which executes programs on your computer. 1 reset mode (0 = soft reset, 1 = hard reset) 0 deturbo mode (82441FX) reserved (82443EX/LX) Note: BIST should not be enabled during a soft reset SeeAlso: #01229,#01129,PORTIBM PC Portable (uses same BIOS as XT) 0CF9h Format of PCI Configuration data for Intel 82454KX/GX: Offset Size Description (Table 01240) 00h 64 BYTEs header (see #00878) (vendor ID 8086h, device ID 84C4h) !!!intel\29052301.pdf pg. 40 40h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. top of system memory 44h 4 BYTEs reserved 48h BYTE PCI decode mode 49h BYTE bridge device number 4Ah BYTE PCI bus number 4Bh BYTE PCI subordinate bus number 4Ch BYTE PB configuration 4Dh 4 BYTEs reserved 51h BYTE deturbo counter control 52h BYTE reserved 53h BYTE CPU(Central Processing Unit) The microprocessor which executes programs on your computer. read/write control 54h WORD PCI read/write control 56h BYTE reserved 57h BYTE SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Enable 58h BYTE video buffer area enable 59h 7 BYTEs Programmable Attribute Map registers 0-6 (see #01118) 60h 16 BYTEs reserved 70h BYTE Error Command 71h BYTE Error Status 72h 6 BYTEs reserved 78h WORD memory gap range 7Ah WORD memory gap upper address 7Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. PCI frame buffer 80h 8 BYTEs reserved 88h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. high memory gap start address 8Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. high memory gap end address 90h 8 BYTEs reserved 98h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (GX only) I/O Space Range #1 9Ch BYTE PCI reset 9Dh 3 BYTEs reserved A0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (GX only) I/O Space Range #2 A4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O APIC range A8h 8 BYTEs reserved B0h WORD configuration values driven on reset B2h 2 BYTEs reserved B4h WORD captured system configuration values (read-only) B6h 2 BYTEs reserved B8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. range BCh BYTE high BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. register BDh 3 BYTEs reserved C0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. PB Extended Error Reporting Command C4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. PB Extended Error Reporting Status C8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. PB Retry Timers CCh 52 BYTEs reserved SeeAlso: #00878