MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000008h - Pentium, PentiumMMX - (TR6) TLB COMMAND
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000007h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000009h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 80000008h


Bitfields for Pentium TLB Command Test Register:
Bit(s)	Description	(Table R0007)
 63-32	reserved (0)
 31-12	linear address
 11	TLB entry is valid
 10	page is dirty (has been written to)
 9	page may only be accessed from Ring 0
 8	page may be written
 7-3	reserved (0)
 2	page is 4M instead of 4K
 1	data TLB instead of code TLB
 0	operation (0=write, 1=read)
SeeAlso: #R0008