MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000009h - Pentium, PentiumMMX - (TR7) TLB DATA Size: 32 bits Access: Read/Write SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000008h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000000Bh,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 80000009h Bitfields for Pentium TLB Data Test Register (TR7): Bit(s) Description (Table R0008) 63-32 reserved (0) 31-12 physical address 11 "CD" Page CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Disable 10 "WB" Page Write-ThroughOne of two main types of caches, the write-through cache immediately writes any new information to the medium it is caching, so that the cache never contains information which is not already present on the cached device. See also cache, 9-7 TLB Least-Recently Used value (non-MMX Pentium only) 6-5 reserved (0) (P54C) 6-5 bits 5-4 of TLB entry number (PentiumMMX only) 4 Hit Indicator 3-0 bits 3-0 of TLB entry number (PentiumMMX only) 3-2 TLB entry number (non-MMX Pentium) 1-0 reserved (0) (non-MMX Pentium) Note: if a write with bit 4 (Hit Indicator) set is followed by a read, the value returned in bit 4 indicates whether the selected address was found in the TLB; if found, bits 3-2 indicate which entry contained the hit SeeAlso: #R0007,#R0009