MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000089h - AMD K6-III - L2AAR (Level 2 CACHE ACCESS REGISTER)
Size:	53 bits


Bitfields for AMD K6-III Level 2 CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Access Register:
Bit(s)	Description	(Table R0072)
 52	"T/D" select tag or data
	=1 access cache tag
	=0 access data
 51-50	reserved
 49-48	way
 47-38	set number
 37	line number
 36-35	octet within line
 34	select high/low DWORDDoubleword; four bytes.	 Commonly used to hold a 32-bit segment:offset or selector:offset address.
 33-32	reserved
---T/D=0 ---
 31-0	data
---T/D=1 ---
 31-15	tag
 14-12	reserved
 11-10	Line1 MESI state
	11 = Modified
	10 = Exclusive
	01 = Shared
	00 = Invalid
 9-8	Line2 MESI state (as for bits 11-10)
 7-0	LRU states (two bits per way)
	00 most recently used
	11 least recently used