MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000082h - AMD K6 - WRITE-HANDLING CONTROL REGISTER Size: 9 bits Note: refer to "AMD-K6™ MMX™ Enhanced Processor Data Sheet", order #20695, http://www.amd.com SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000080h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000081h Bitfields for AMD K6 Write-Handling Control Register: Bit(s) Description (Table R0061) ---AMD K6 prior to model 8,step 8--- 63-9 reserved 8 write cacheability detection enabled Note: the Intel Triton chipset does not support write cacheability detection, so this bit should be kept clear 7-1 write allocate enable limit (in 4M units) memory above this limit will not be accessed without a write-allocate 0 write allocate enabled for 15-16M region ---AMD K6 model 8,step 8 and later--- 63-32 reserved 31-22 Write Allocation enable limit, in 4MB units 21-17 reserved 16 enable Write Allocation for 15MB-16MB 15-0 reserved --------------------------------------------- MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000085h - AMD K6-2 - "UWCCR" UC/WC Cacheability Control Register Size: 64 bits Access: Read-Write Note: available on the K6-III and K6-2 Step 8 or higher SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000087h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000088h Bitfields for AMD K6 UC/WC Cacheability Control Register: Bit(s) Description (Table R0067) 63-49 "PHYS_BASE1" Physical Address Base # 1, 128 KB and range size-aligned 48-34 "PHYS_MASK1" Physical Address Mask # 1, in units of 128KB 33 "WC1" Write Combinbing # 1 =1 enabled/uncachable =0 disabled 32 "UC1" Uncacheble #1 =1 uncachable =0 disabled 31-17 "PHYS_BASE0" 16-2 "PHYS_MASK0" Physical Address Mask # 1, in units of 128KB 1 "WC0" write combining #0 0 "UC0" uncacheable #0 SeeAlso: #R0068 --------------------------------------------- MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000087h - AMD K6-2 - "PSOR" Processor State Observability Register Size: 8 bits Access: Read-Only SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000085h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000088h Bitfields for AMD K6 Processor State Observability Register: Bit(s) Description (Table R0068) 63-9 reserved 8 "NOL2" (No L2 functionallity) 7-4 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. stepping 3 reserved 2-0 "BF" Bus Frequency Divisor 000 = x4.5 100 = x2.5 001 = x5.0 101 = x3.0 010 = x4.0 110 = x6.0 011 = x5.5 111 = x5.5 SeeAlso: #R0067,#R0069 --------------------------------------------- MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000088h - AMD K6-2 - "PFIR" Page FlushTo force the copying of any data still stored in temporary buffers to its final destination./Invalidate Register Size: 32 bits SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000085h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. C0000087h Bitfields for AMD K6-2 Page FlushTo force the copying of any data still stored in temporary buffers to its final destination./Invalidate Register: Bit(s) Description (Table R0069) 63-32 reserved 31-12 "LINPAGE" linear 4KB page address 11-9 reserved 8 "PF" page fault occured 7-1 reserved 0 "F/I" FlushTo force the copying of any data still stored in temporary buffers to its final destination./Invalidate command (=1 invalidate, =0 flush) SeeAlso: #R0068