PORTIBM PC Portable (uses same BIOS as XT) 03D4-03D5 - COLOR VIDEO - CRT CONTROL REGISTERS

03D4  rW  CRT (6845) register index   (CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA./MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines./color EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./color VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.)
	selects which register (0-11h) is to be accessed through 03D5
	this port is r/w on some VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers., e.g. ET4000
	    bit 7-6 =0: (VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) reserved
	    bit 5   =0: (VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) reserved for testage
	    bit 4-0   : selects which register is to be accessed through 03D5
03D5  -W  CRT (6845) data register   (CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA./MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines./color EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./color VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) (see #P0708)
	selected by PORTIBM PC Portable (uses same BIOS as XT) 03D4h. registers 0C-0F may be read
	  (see also PORTIBM PC Portable (uses same BIOS as XT) 03B5h)
	MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines., native EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors. and VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. use very different defaults from those
	  mentioned for the other adapters; for additional notes and
	  registers 00h-0Fh and EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. registers 10h-18h and ET4000
	  registers 32h-37h see PORTIBM PC Portable (uses same BIOS as XT) 03B5h (see #P0654)
	registers 10h-11h on CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA., EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors., VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. and 12h-14h on EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors., VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. are
	  conflictive with MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. (see #P0710)


(Table P0708)
Values for EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./VGA+ CRT Controller register index:
 00h-0Fh	same as MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also CGAColor Graphics Adapter, HGC./CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA. (see #P0654)
 10h R-	native VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. with bit7=1 in end horizontal blanking (03h) and ET4000:
	       start vertical retrace
 10h -W start vertical retrace
 11h R- native VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. with bit7=1 in end horizontal blanking (03h):
	       end vertical retrace
 11h -W end vertical retrace
	       bit7  : VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.: protection bit
			    =0 enable write access to 00h-07h
			    =1 read only regs 00h-07h with the exception
			       of bit4 in 07h. ET4000: protect 35h also.
	       bit6  : VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.: =0 three, =1 five refreshcycles/line
		       ET4000: reserved
	       bit5=0: (MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. also) enable vertical interrupt
	       bit4=0: (MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. also) clear vertical interrupt
		   =1:		   no effect
	       bit3-0: (MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. also) vertical retrace end
 12h	vertical display end register
 13h	row offset register
	       logical screen line width in
		byte mode : bytes/(line/2)
		word mode : bytes/(line/4)
		dword mode: bytes/(line/8)
 14h	underline location register
	       bit7: reserved (0)
	       bit6: (VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) 0=word-mode, 1=dword-mode (see 17h, bit6)
	       bit5: (VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) 0=standard address counter clock
			   1=address counter clock/4 (see 17h, bit3)
	       bit4-0: horizontal underline row scan
 15h	(EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors.,VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) start vertical blanking-1
 16h	(EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors.,VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) end vertical blanking register
	       bit7-5 : EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors.: reserved, but used on original EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors.???
	       bit4-0 : end vertical blanking
 17h	(EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors.,VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) "CR17" mode control register (see #P0657)
 18h	(EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors.,VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) "CR18" line compare register
 19h	Genoa SuperEGA only: double scan control
	       at 3B5h only in MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also CGAColor Graphics Adapter, HGC., HGC(Hercules Graphics Card) A monochrome video adapter capable of 720x352 monochrome graphics.	 The HGC was the first non-IBM video adapter for the IBMInternational Busiuness Machines PCIBM PC.	 See also CGAColor Graphics Adapter, MDA. emulation, but at 3D5h even in
	       mono EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors. modes.
	       bit7-5 : reserved
	       bit4   : HR/VR width adjust flag for double scan mode
	       bit3-1 : 1=test, 0=normal
	       bit0   : double scan enable
 1Dh	Elsa Victory Erazor only: video page select for writing
		bits 7-1 = offset into video memory in 64K units
		bit 0: ???
 1Eh	Elsa Victory Erazor only: video page select for reading
		bits 7-1 = offset into video memory in 64K units
		bit 0: ???
 22h	(VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) "CR22" CPU(Central Processing Unit) The microprocessor which executes programs on your computer. Latch Data Register (read-only)
 24h	(VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) "CR24" Attribute Controller Toggle register (R-O) (see #P0709)
 3xh	(VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.)  !!!chips\64200.pdf p.57
Notes:	registers 10h-14h on the MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. have conflicting uses (see #P0710)
	registers 22h,24h, and 3xh exist on the standard IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. but were not
	  documented
SeeAlso: #P0756,#P0716,#P0717


Bitfields for VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. "CR24" Attribute Controller Toggle register:
Bit(s)	Description	(Table P0709)
 7-3	current attribute controller index
 2	palette address source
 1	reserved
 0	state of attribute-controller flip-flop (0 = index, 1 = data)
Note:	this register was not documented for the original IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.; this
	   description is from the C&T Wingine documentation
SeeAlso: #P0708,#P0718


(Table P0710)
Values for MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. (only) CRT Controller register index:
 00h-0Fh	same as MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also CGAColor Graphics Adapter, HGC./CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA. (see #P0654)
 10h -W mode control register (defaults 18h, 1Ah, 19h) (see #P0711)
 10h R-	mode control status register (see #P0712)
 11h -W	interrupt control register (default 30h) (see #P0713)
 12h RW	character generator/sync polarity register (see #P0714)
 12h R-	display sense register (int. control reg [11h] bit7=1)
	bit 7-2	 : not used
	bit 1-0	 : pins 11 & 12 in monitor cable
		00b = reserved
		01b = analogue monochrom monitor
		10b = analogue color graphics monitor
		11b = no monitor
 13h -W character font pointer register (see #P0710)
	only 00h, 10h, 20h, 30h (default 00h) are allowed here
	  for textmode fonts at A0000, A2000, A4000, A6000
 14h -W	number of characters to load during vert. retrace period (default FFh)
Note:	registers 10h-14h can appear at PORTIBM PC Portable (uses same BIOS as XT) 03D5h only, not at 03B5h
SeeAlso: #P0654,#P0708,#P0756,#P0715


Bitfields for MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. (only) CRT mode control register:
Bit(s)	Description	(Table P0711)
 7	suppress hsync/vsync
 6	reserved (0)
 5	reserved
 4	dot clock rate
 3	refresh calculations in 80x25 modes
 2	reserved
 1	videomode 11h active
 0	videomode 13h active
SeeAlso: #P0710,#P0712


Bitfields for MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. (only) CRT mode control status register:
Bit(s)	Description	(Table P0712)
 7	status bit0 CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA. mode control register
 6	reserved
 5	clockrate 640 pixel, =0: clockrate/2 320 pixel
 4	clock rate is 25,175Mhz
 3	currently in textmode
 2	double-scan activated
 1	videomode 11h active
 0	videomode 13h active
SeeAlso: #P0710,#P0711


Bitfields for MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. (only) CRT interrupt control register:
Bit(s)	Description	(Table P0713)
 7	set output driver to tristate
	=0: for reading of character generator reg (12h)
	=1: for reading of display sense register (12h)
 6   R	intr generated by memory controller
 5	=0 requested intr ok to handle
 4	=0 free interrupt latch register
 3-0	reserved
SeeAlso: #P0710


Bitfields for MCGAMulti-Color Graphics Array(Multi-Color Graphics Array) The low-end color adapter offered in IBMInternational Busiuness Machines's early PS/2IBM PS/2, any model series machines. (only) CRT character generator/sync polarity register:
Bit(s)	Description	(Table P0714)
 7	character generator active
 6	=1 load codepage during display
	=0 load codepage during retrace
 5	codepage number (0,1)
 4	512 characters active
 3	reserved (0)
 2	enable hsync/vsync
 1	positive vsync polarity
 0	positive hsync polarity
Note:	default 46h in all modes, except 04h in mode 11h)
SeeAlso: #P0710
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 03D4-03D5 - Chips&Technologies VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 03D4h"COLOR VIDEO",PORTIBM PC Portable (uses same BIOS as XT) 03D4h"Tseng"

03D4  RW  CRT control register index (see #P0715)
03D5  RW  CRT control register value


(Table P0715)
Values for Chips&Technologies CRT Controller register index:
 00h-18h same as EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
 22h	same as VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
 24h	same as VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
---C&T 82C4xx---
 D3h RW "RD3" 82C426: gray-level control 1 !!!chips\82c426.pdf p.16
 D4h RW "RD4" 82C426: gray-level control 2
 D5h RW "RD5" 82C426: general purpose
 D6h RW "RD6" 82C426: sleep
 D7h RW "RD7" 82C426: panel size
 D8h RW "RD8" 82C426: panel configuration
 D9h RW "RD9" AC control   !!!chips\82c425.pdf p.27
 DAh RW "RDA" threshold
 DBh RW "RDB" shift parameter
 DCh RW "RDC" horizontal sync width
 DDh RW "RDD" vertical sync width / blink control
 DEh RW "RDE" timing control
 DFh RW "RDF" function control
SeeAlso: #P0654,#P0710,#P0756,#P0716
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 03D4-03D5 - Cirrus Logic VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 03D4h"COLOR VIDEO",PORTIBM PC Portable (uses same BIOS as XT) 03D4h"Tseng"

03D4  RW  CRT control register index (see #P0716)
03D5  RW  CRT control register value


(Table P0716)
Values for Cirrus Logic CRT Controller register index:
 00h-18h same as EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
---Cirrus CL-GD7556---
 19h	"CR19" Interlace End
 1Ah	"CR1A" miscellaneous control
 1Bh	"CR1B" extended display control
 1Ch	"CR1C" horizontal total and sync
 1Dh	"CR1D" color key compare type
 22h	same as VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
 24h	same as VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
 25h	"CR25" revision
 26h	"CR26" attribute controller index readback
 27h	"CR27" device identification
 30h	"CR30" TV-OUT control
 31h	"CR31" Video Window horizontal upscaling coefficient
 32h	"CR32" Video Window vertical upscaling coefficient
 33h	"CR33" Video Window horizontal start (high)
 34h	"CR34" Video Window horizontal start (low)
 35h	"CR35" Video Window brightness
 36h	"CR36" Video Window vertical position extension
 37h	"CR37" Video Window vertical start
 38h	"CR38" Video Window vertical height
 ...
 42h	"CR42" Video Window FIFO threshold / chroma-key mode
 50h	"CR50" V-Port hardware configuration
 ...
 5Fh	"CR5F" V-Port capture window start address (low)
 80h	"CR80" power management control
 ...
 91h	"CR91" shading map offset
 A0h	"CRA0" CRT horizontal 8-dot character clock
 ...
 BFh	"CRBF" CRT vertical back porch
!!! details to be added
SeeAlso: #P0654,#P0756,#P0717
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 03D4-03D5 - S3 VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 03D4h"COLOR VIDEO",PORTIBM PC Portable (uses same BIOS as XT) 03D4h"Tseng"

03D4  RW  CRT control register index (see #P0717)
03D5  RW  CRT control register value


(Table P0717)
Values for S3, Inc. CRT Controller register index:
 00h-18h same as EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
 22h	same as VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
 24h	"CR24" attribute controller index/data status
 26h R- "CR24" (duplicate of 24h)
 2Dh R- "CR2D" new Chip ID (high) (same as high byte of PCI device ID)
 2Eh R- "CR2E" new chip ID (low) (same as low byte of PCI device ID)
		10h Trio32
		11h Trio64
 2Fh R- "CR2F" S3 7xx/866/x68: chipset revision
		chip ID 8811h is Trio64/64V+; revision 4xh or 5xh is Trio64V+
 30h RW	"CR30" chip ID/revision (see #P0719)
 31h RW	"CR31" memory configuration (see #P0720)
 32h RW "CR32" backward compatibility 1 (see #P0721)
 33h RW "CR33" backward compatibility 2 (see #P0722)
 34h RW "CR34" backward compatibility 3 (see #P0723)
 35h RW "CR35" CRT register lock (see #P0724)
 36h R	"CR36" Reset State read 1 (see #P0725)
 37h R	"CR37" Reset State read 2 (see #P0726)
 38h RW	"CR38" S3 Register lock 1
	set reg 38h to 48h and reg 39h to A5h to unlock other S3 registers
 39h RW	"CR39" S3 Register lock 2
 3Ah RW "CR3A" S3 Miscellaneous 1 (see #P0727)
	bit 4: ???
 3Bh RW "CR3B" Data Transfer Execute position (see #P0728)
 3Ch RW "CR3C" Interlace Retrace start position (see also #P0730)
 40h RW "CR40" System Configuration (see #P0729)
 41h	"CR41" BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Flag register (used by S3 BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.)
 42h RW "CR42" mode control (see #P0730)
 43h RW "CR43" extended mode (see #P0731)
 45h RW "CR45" hardware graphics cursor mode (see #P0732)
 46h RW "CR46" hardware cursor origin X (hi), bits 2-0 only
 47h RW "CR47" hardware cursor origin X (lo)
	testing that register 47h can be read and written once the S3 registers
	  are unlocked is used as an S3 installation check
 48h RW	"CR48" hardware cursor origin Y (hi), bits 2-0 only
	the cursor X/Y position is latched on writing the high byte of Y
 49h RW "CR49" hardware cursor origin Y (lo)
 4Ah RW "CR4A" hardware graphics cursor foreground stack
	read register 45h, then write 2 or 3 color bytes (16/24-bit color)
	  to specify foreground color of hardware cursor
 4Bh RW "CR4B" hardware graphics cursor background stack
	read register 45h, then write 2 or 3 color bytes (16/24-bit color)
	  to specify background color of hardware cursor
 4Ch RW "CR4C" hardware graphics cursor map start address (hi), bits 3-0 only
 4Dh RW "CR4D" hardware graphics cursor map start address (lo)
 4Eh RW "CR4E" hardware cursor pattern start X (bits 5-0 only)
 4Fh RW "CR4F" hardware cursor pattern start Y (bits 5-0 only)
 50h RW "CR50" S3 801+: Extended System Control 1 (see #P0733)
 51h RW "CR51" S3 801+: Extended System Control 2 (see #P0734)
 52h RW "CR52" S3 801+: Extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Flag 1
		bits 7-6 are sync polarities (see #P0669) for Diamond cards
 53h RW "CR53" S3 801+: Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 1 (see #P0735)
 54h RW "CR54" S3 801+: Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 2 (see #P0736,#P0737)
 55h RW "CR55" S3 801+: Extended Video DAC(Digital-to-Analog Converter) A hardware device (in its simplest form, nothing more than a set of interconnected resistors) which converts a digital number into an analog signal whose voltage is proportional to the value of the digital number.  VGAVideo Graphics Array and later color video boards use DACs to convert color values into the analog signals sent to the display; sound boards normally use DACs as well. Control (see #P0738)
 56h RW "CR56" S3 801+: External Sync Control 1 (see #P0739)
 57h RW "CR57" S3 801+: External Sync Control 2 (see #P0740)
 58h RW "CR58" S3 801+: Linear Address Window Control (see #P0741)
 59h RW "CR59" S3 801+: Linear Address Window Position (bits 31-24)
 5Ah RW "CR5A" S3 801+: Linear Address Window Position (bits 23-16)
	Notes:	the address is forced to be a multiple of the memory window
		  size (see #P0741) by ignoring the lowest bits
		for Trio64 new memory-mapped I/O, the LAW must be on a 64M
		  boundary
 5Bh RW "CR5B" S3 801+: Extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Flag 2
 5Ch RW "CR5C" S3 801+: General Output Port (see #P0742)
 5Dh RW "CR5D" S3 801+: Extended Horizontal Overflow (see #P0743)
 5Eh RW "CR5E" S3 801+: Extended Vertical Overflow (see #P0744)
 5Fh RW "CR5F" S3 928/964: Bus Grant Termination Position
 60h RW "CR60" S3 864/964: extended memory control 3 (see #P0745)
 61h RW "CR61" S3 864/964/Trio: extended memory control 4 (see #P0746)
 62h RW "CR62" S3 864/964: extended memory control 5
 63h RW "CR63" S3 864/964: external sync delay adjustment (high) (see #P0747)
 64h RW "CR64" S3 864/964: genlocking adjustment
 65h RW "CR65" S3 864/964: extended miscellaneous control (see #P0748)
 66h RW "CR66" S3 864/964: extended miscellaneous control 1 (see #P0749)
 67h RW "CR67" S3 864/964: extended miscellaneous control 2 (see #P0750)
 67h RW "CR67" S3 Trio32/64: extended miscellaneous control 2 (see #P0751)
 68h RW "CR68" S3 864/964: configuration 3 (see #P0752)
 69h RW "CR69" S3 864/964: extended system control 3 (see #P0753)
 6Ah RW "CR6A" S3 864/964: extended system control 4
		(bits 5-0 = offset of 64K bank)
 6Bh RW "CR6B" S3 864/964: extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. flag 3
 6Ch RW "CR6C" S3 864/964: extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. flag 4
 6Dh RW "CR6D" S3 864/964: extended miscellaneous control
 6Dh RW "CR6D" S3 Trio64V+: extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. flag 5 (reserved for BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.)
 6Eh RW "CR6E" S3 Trio64V+: extended BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. flag 6 (reserved for BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.)
 6Fh RW "CR6F" S3 Trio64V+: configuration 4 (see #P0755)
SeeAlso: #P0654,#P0710,#P0756,#P0716,#P0715


Bitfields for S3 "CR24" Attribute Index register:
Bit(s)	Description	(Table P0718)
 7	inverse of current state of internal address flip-flop
 6	reserved (0)
 5	video display is enabled (mirror of PORTIBM PC Portable (uses same BIOS as XT) 03C0h bit 5)
 4-0	current attribute contorller index (from PORTIBM PC Portable (uses same BIOS as XT) 03C0h)
SeeAlso: #P0708,#P0709,PORTIBM PC Portable (uses same BIOS as XT) 03C0h


(Table P0719)
Values for S3 chip ID/Revision register "CR30":
 81h	86c911
 82h	86c911A/924
 90h	86c928 (original)
 ...
 A0h	86c801/805 A-step or B-step
 ...
 B0h	86c928 PCI
 C0h	Vision864
 C1h	Vision864P
 D0h	Vision964
 D1h	Vision964P
 Exh	Trio32/64, 86c866, 86c868, 86c968; actual ID and revision stored in
	  PORTIBM PC Portable (uses same BIOS as XT) 03B5h registers 2Dh, 2Eh, and 2Fh
SeeAlso: #P0720


Bitfields for S3 "CR31" memory configuration register:
Bit(s)	Description	(Table P0720)
 7	(except 864/964) enable BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. address space C6800h-C7FFFh
	(Trio64V+) reserved
 6	enable page-mode memory access for text-mode font access
 5-4	display start address, bits 17&16.  See also registers 51h and 69h
 3	video memory above 256K accessible
 2	VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. 16-bit memory bus (clear for 8-bit memory bus)
 1	two-page screen image (enables 2048-pixel wide screen)
 0	enable base-address offset (turn on bank-switched operation)
SeeAlso: #P0708,#P0719,#P0721


Bitfields for S3 "CR32" Backwards Compatibility 1 register:
Bit(s)	Description	(Table P0721)
 7	(928,964) tri-state serial output pins SC, SOE0, and SXNR
 6	fix VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. screen page using display start address bits 16&17 (see #P0720)
	(Trio64V+) force wrap on 256K boundary even when display start address
	  changed
 5	???
 4	enable hardware interrupts
 3	backward-compatible modes (set for MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also CGAColor Graphics Adapter, HGC./CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA./EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./HGC(Hercules Graphics Card) A monochrome video adapter capable of 720x352 monochrome graphics.	 The HGC was the first non-IBM video adapter for the IBMInternational Busiuness Machines PCIBM PC.	 See also CGAColor Graphics Adapter, MDA.)
 2	force full character clock for horizontal timing (CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA./HGC(Hercules Graphics Card) A monochrome video adapter capable of 720x352 monochrome graphics.	 The HGC was the first non-IBM video adapter for the IBMInternational Busiuness Machines PCIBM PC.	 See also CGAColor Graphics Adapter, MDA. emulation),
	  rather than 1/2 dot clock rate
 1-0	character clock period
	00 IBM-compatible, 8 or 9 dots
	01 7 dots
	10 9 dits
Note:	on the Trio64V+, bits 7, 5, and 3-0 are reserved
SeeAlso: #P0720,#P0722,#M0076


Bitfields for S3 "CR33" Backwards Compatibility 2 register:
Bit(s)	Description	(Table P0722)
 7	override CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC.  See also HGC, MDA. "enable video" at PORTIBM PC Portable (uses same BIOS as XT) 03D8h bit 3
 6	lock palette/overscan registers
 5	blank signal does not include border area, is same as display enable
 4	disable writes to RamDAC
 3	VCLK is internal DCLK rather than inverted DCLK/2 or external VCLK
 2	reserved (Trio32/64)
 1	disable VDE protection (PORTIBM PC Portable (uses same BIOS as XT) 03D4h register 11h bit 7 will not act
	  on PORTIBM PC Portable (uses same BIOS as XT) 03D4h register 7h bits 1 and 6)
 0	reserved (Trio32/64)
Note:	on the Trio64V+, bits 7, 2, and 0 are reserved
SeeAlso: #P0708,#P0721,#P0723


Bitfields for S3 "CR34" Backwards Compatibility 3 register:
Bit(s)	Description	(Table P0723)
 7-5	(Trio32/64/64V+) reserved
 7	lock PORTIBM PC Portable (uses same BIOS as XT) 03C2h bits 2,3
 5	lock SR1 bit 5
 4	enable Start Display FIFO Fetch register (CR3B) (see #398)
 3	(Trio32/64/64V+) reserved
 2	PCI retries not handled during DAC(Digital-to-Analog Converter) A hardware device (in its simplest form, nothing more than a set of interconnected resistors) which converts a digital number into an analog signal whose voltage is proportional to the value of the digital number.  VGAVideo Graphics Array and later color video boards use DACs to convert color values into the analog signals sent to the display; sound boards normally use DACs as well. cycles (requires bit 0 clear)
 1	do not handle PCI master aborts during DAC(Digital-to-Analog Converter) A hardware device (in its simplest form, nothing more than a set of interconnected resistors) which converts a digital number into an analog signal whose voltage is proportional to the value of the digital number.  VGAVideo Graphics Array and later color video boards use DACs to convert color values into the analog signals sent to the display; sound boards normally use DACs as well. cycles (requires bit 0 clear)
 0	disable PCI master aborts/retries during DAC(Digital-to-Analog Converter) A hardware device (in its simplest form, nothing more than a set of interconnected resistors) which converts a digital number into an analog signal whose voltage is proportional to the value of the digital number.  VGAVideo Graphics Array and later color video boards use DACs to convert color values into the analog signals sent to the display; sound boards normally use DACs as well. cycles
SeeAlso: #P0722,#P0724


Bitfields for S3 "CR35" Register Lock register:
Bit(s)	Description	(Table P0724)
 7-6	(Trio32/Trio64) reserved
 5	lock horizontal timing registers
 4	lock vertical timing registers
 3-0	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. base address (in 64K units), bits 17-14
SeeAlso: #P0708,#P0723,#P0725


Bitfields for S3 "CR36" Configuration 1 register:
Bit(s)	Description	(Table P0725)
 7-5	video memory size
	111 less than 1M
	110 one meg
	100 two megs
	010 three megs
	000 four megs
	101 six megs
	011 eight megs
 4	(Trio32/64, VL-Bus only) enable video BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. accesses
 3-2	(Trio32/64) memory type
	00 reserved
	01 reserved
	10 EDO
	11 fast page mode
 1-0	(Trio32/64) system bus type
	00 reserved
	01 VESA(Video Electronics Standards Association)  An industry group which sets both hardware and software standards and recommendations. The term VESA is also used to denote compliance with the VESA SuperVGA BIOS Extensions, a standard set of video BIOS functions for accessing video modes of higher resolution than those defined by IBMInternational Busiuness Machines. local bus
	10 PCI
	11 reserved
Note:	the default value of this register is latched from external pins at
	  power-up; bits 1-0 are read-only
SeeAlso: #P0708,#P0724,#P0726


Bitfields for S3 "CR37" Configuration 2 register:
Bit(s)	Description	(Table P0726)
 7-5	monitor type
 7-5	(Trio64V+) reserved
 4	(VL-Bus) enable RAMDAC write snooping
 3	use internal DCLK/MCLK (clear this bit for testing only)
 2	(VL-Bus) video BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. size (=0 64K, =1 32K)
 1	test mode select (=0 tri-state all outputs, =1 normal operation)
 1	(Trio64V+) reserved
 0	(VL-Bus) enable Trio chip (if 0, disabled except for video BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. access)
Notes:	the default value of this register is latched from external pins at
	  power-up
	the description of this register is based on the Trio32/Trio64/Trio64V+
	  documentation and may vary somewhat for other S3 chips
SeeAlso: #P0708,#P0725


Bitfields for S3 "CR3A" Miscellaneous 1 register:
Bit(s)	Description	(Table P0727)
 7	disable PCI burst read cycles
	(must set CR66 bit 7 before setting this bit)
 6	reserved
 5	enable high-speed text font writes (only required for DCLK > 40MHz)
 4	enable >= 8 bpp color enhanced modes
 3	enable top-of-memory access (simultaneous VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. text and enhanced mode)
 2	enable alternate refresh count control (bits 1-0)
	when enabled, bits 1-0 override CR11 bit 6
 1-0	alternate refresh count: number of refresh cycles per scan line
Note:	the description of this register is based on the Trio32/Trio64/Trio64V+
	  documentation and may vary somewhat for other S3 chips
SeeAlso: #P0708


Bitfields for S3 "CR3B" Start Display FIFO Register:
Bit(s)	Description	(Table P0728)
 7-0	bits 7-0 of time in characters clocks from start of active display
	  until FIFO data fetching restarts after start of horizontal blanking
	  (bit 8 is in CR5D bit 6)
Note:	the value for this register is typically CR0 less 5, and helps ensure
	  adequate time for RAM(Random Access Memory)	See also DRAM, SRAM. refresh, etc. taht require control of display
	  memory
SeeAlso: #P0708


Bitfields for S3 "CR40" System Configuration register:
Bit(s)	Description	(Table P0729)
 7-6	reserved (0)
 5	reserved ("WDL_DELAY") (1)
 4	(VL-Bus) Ready Control
	=0 zero wait-states from -SADS to -SRDY
	=1 minimum one wait state (controlled by CR58 bit 3)
 3-1	reserved (0)
 0	enable enhanced (8514/A superset) register access at PORTIBM PC Portable (uses same BIOS as XT) x2E8h
SeeAlso: #P0708


Bitfields for S3 "CR42" Mode Control register:
Bit(s)	Description	(Table P0730)
 7-6	reserved (0)
 5	interlaced video
 4-0	reserved
Note:	bit 5 also enables CR3C
SeeAlso: #P0708,#P0731


Bitfields for S3 "CR43" Extended Mode register:
Bit(s)	Description	(Table P0731)
 7	double horizontal CRT parameters (CRTC registers 00h, etc.)
 6-3	reserved (0)
 3	(Trio64V+) ??? used by BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly., officially reserved
 2	logical screen width (CR13), bit 8
 1-0	reserved (0)
Note:	bit 2 is disabled unless CR51 bits 5-4=00
SeeAlso: #P0708,#P0730


Bitfields for S3 "CR45" Hardware Graphics Cursor Mode register:
Bit(s)	Description	(Table P0732)
 7-5	reserved (0)
 4	enable Hardware Cursor Right Storage (last 256 bytes of 1K line, or
	  last 512 bytes of 2K line)
 3-1	reserved (0)
 0	enable hardware graphics cursor in Enhanced (8514/A) mode
SeeAlso: #P0708


Bitfields for S3 "CR50" Extended System Control 1 register:
Bit(s)	Description	(Table P0733)
 7-6	Graphics Engine screen width
	(note: bit 0 below is MSB for the following)
	000 = 1024 (2048 if CR31 bit 1 set)
	001 = 640
	010 = 800 (1600x1200x4 if PORTIBM PC Portable (uses same BIOS as XT) 4AE8h bit 2 set)
	011 = 1280
	100 = 1152
	101 reserved
	110 = 1600
	111 reserved
 5-4	pixel length for command execution through Graphics Engine (8514/A)
	00 one byte (4 or 8 bits/pixel)
	01 two bytes (16 bpp)
	10 reserved
	11 four bytes (32 bpp)
 3	reserved (0)
 2	enable -BREQ/-BGNT functions (reserved on Trio64V+)
 1	reserved (0)
 0	bit 2 of Graphics Engine screen width (refer to bits 7-6 above)
SeeAlso: #P0708,#P0735,#P0734


Bitfields for S3 "CR51" Extended System Control 2 register:
Bit(s)	Description	(Table P0734)
 7-6	reserved (0)
 5-4	logical screen width, bits 9-8
 3-2	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. base address, bits 19-18
 1-0	display start address, bits 19-18
Notes:	if the upper four bits of the display start address have been set via
	  CR69 bits 3-0, then bits 1-0 and CR31 bits 5-4 are ignored
	if the upper 6 base address bits have been set via CR6A bits 5-0, then
	  bits 3-2 and CR35 bits 3-0 are ignored
SeeAlso: #P0708,#P0733


Bitfields for S3 "CR53" Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 1 register:
Bit(s)	Description	(Table P0735)
 7	reserved
 6	(Trio32/64/64V+) swap nybbles in each byte of video memory read or
	  written
 5	(801/805) memory interleaving
	(928) pixel multiplexing
	(Trio64V+) enable memory-mapped I/O at B8000h-BFFFFh instead of
	  A0000h-AFFFFh (only takes effect if bits 4-3=10)
 4	enable memory-mapped I/O (Trio32, Trio64 and Trio64V+)
 3	enable new memory-mapped I/O (Trio64V+)
 2-1	(Trio64V+) byte swapping for linear addressing
	00 none (default)
	01 swap bytes of word
	10 swap all bytes of doublewords
	11 reserved
	(used for big-endian addressing)
 0	(Trio32/64) enable write per bit
	(Trio64V+) reserved
SeeAlso: #P0708,#P0736


Bitfields for S3 Trio32/64 "CR54" Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 2 register:
Bit(s)	Description	(Table P0736)
 7-3	"M" number of 8-byte memory cycles not dedicated to filling display
	  FIFO (less one)
 2-0	reserved (0)
SeeAlso: #P0737,#P0708,#P0735


Bitfields for S3 Trio64V+ "CR54" Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 2 register:
Bit(s)	Description	(Table P0737)
 2,7-3	"M" maximum number of 8-byte memory cycles before LPB/CPU(Central Processing Unit) The microprocessor which executes programs on your computer./Graphics
	  Engine must yield the memory bus
 1-0	big-endian byte-swapping (except for linear addressing/image writes)
	00 none (default)
	01 swap bytes within a word
	10 swap all bytes within a doubleword
	11 swap according to bus' byte-enable lines
		BE#[3:0]=0000 swap all bytes
		BE#[3:0]=0011 or 1100 swap bytes within selected word
		else no swapping
SeeAlso: #P0708,#P0736 


Bitfields for S3 "CR55" Extended RAMDAC Control register:
Bit(s)	Description	(Table P0738)
 7	tri-state VCLK output
 6-5	reserved (0)
 4	hardware cursor mode
	=0 MS-Windows
	=1 X11
 3	reserved (0)
 2	enable General Input Port read (at PORTIBM PC Portable (uses same BIOS as XT) 03C8h)
 1-0	reserved (0)
SeeAlso: #P0708


Bitfields for S3 "CR56" External Sync Control 1 register:
Bit(s)	Description	(Table P0739)
 7-5	reserved (0)
 4	preset frame select
	=0 start with odd frame after V-counter reset
	=1 start with even frame
 3	reset only vertical counter on falling edge of VSYNC input when
	  genlocking
 2	tri-state VSYNC output
 1	tri-state HSYNC output
 0	enable VSYNC input for genlocking
Note:	bits 4-3 are reserved on the Trio64V+
SeeAlso: #P0708,#P0740


Bitfields for S3 "CR57" External Sync Control 2 register:
Bit(s)	Description	(Table P0740)
 7-0	delay in scan lines from falling edge of VSYNC to reset of V-counter
Note:	this register must NOT be 00h when genlocking is enabled (CR56 bit 0)
SeeAlso: #P0708,#P0739


Bitfields for S3 "CR58" Linear Addressing Control register:
Bit(s)	Description	(Table P0741)
 7	RAS Pre-Charge time adjust
	=0 CR68 bit 3 defines pre-charge time
	=1 decrease pre-charge time by 0.5 MCLKs, increase RAS time by 0.5 MCLKs
 6-5	reserved
 4	enable linear addressing (see also #P1022)
 3	(VL-Bus) addresses latched in T1 cycle, instead of delaying one clock
	  until T2 cycle; only in effect when CR40 bit 4 is set
 2	reserved
 1-0	linear address window size
	00 = 64K (not available when new MMIO enabled)
	01 = 1M
	10 = 2M
	11 = 4M (Trio64/64V+, not Trio32)
Note:	this description is based on the Trio32/Trio64 documenation; the
	  bits may vary slightly for other S3 chips
SeeAlso: #P0723


Bitfields for S3 "CR5C" General Output Port:
Bit(s)	Description	(Table P0742)
 7-0	system-specific
---Diamond---
 0	???
 1	???
---STB Pegasus---
 7	map video memory with bits 31-26 = 011111
SeeAlso: #P0708


Bitfields for S3 "CR5D" Extended Horizontal Overflow register:
Bit(s)	Description	(Table P0743)
 7	bit 8 of Bus-Grant Terminate Position (CR5F)
	(Trio64V+) reserved
 6	bit 8 of Start FIFO Fetch (CR3B)
 5	extend horizontal sync pulse by 32 DCLKs
 4	bit 8 of Start Horizontal Sync Position (CR4)
 3	extend horizontal blank pulse by 64 DCLKs
 2	bit 8 of Start Horizontal Blank (CR2)
 1	bit 8 of Horizontal Display End (CR1)
 0	bit 8 of Horizontal Total (CR0)
SeeAlso: #P0708,#P0744


Bitfields for S3 "CR5E" Extended Vertical Overflow register:
Bit(s)	Description	(Table P0744)
 7	reserved (0)
 6	line compare position (CR18), bit 10
 5	reserved (0)
 4	vertical retrace start (CR10), bit 10
 3	reserved (0)
 2	start of vertical blank (CR15), bit 10
 1	vertical display end (CR12), bit 10
 0	vertical total (CR6), bit 10
SeeAlso: #P0708,#P0743


Bitfields for S3 Trio32/64 "CR60" Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 3 register:
Bit(s)	Description	(Table P0745)
 7-0	"N" maximum number of 4-byte (1M video memory) or 8-byte (2M/4M) units
	  written to display FIFO in an uninterruptible burst
SeeAlso: #P0708,#P0746


Bitfields for S3 Trio64V+ "CR61" Extended MemoryMemory beyond the one megabyte address which is available only on 80286 and higher machines.  Except for a small portion (the High Memory Area), extended memory is only accessible from protected mode. Control 4 register:
Bit(s)	Description	(Table P0746)
 7	reserved
 6-5	byte-swapping for image writes
	00 none (default)
	01 swap bytes within each word
	10 swap all bytes within a doubleword
	11 reserved
 4-0	reserved
SeeAlso: #P0708,#P0745


Bitfields for S3 Trio32/64 "CR63" External Sync Control 3 register:
Bit(s)	Description	(Table P0747)
 7-4	character clock reset delay
 3-0	HSYNC reset adjustment, in character clocks
Notes:	these two values are used to align the external and internally-generated
	  video during genlocking
	this register is not documented for the Trio64V+, and may not exist
SeeAlso: #P0708


Bitfields for S3 Trio32/64/64V+ "CR65" Extended Miscellaneous Control register:
Bit(s)	Description	(Table P0748)
 7-5	reserved (0)
 4-3	(Trio32/64V+) delay -BLANK by N DCLKs
	a two-DCLK delay is required for color mode 12
 2	video subsystem setup address
	(Trio64V+) reserved
	=0 PORTIBM PC Portable (uses same BIOS as XT) 46E8h
	=1 PORTIBM PC Portable (uses same BIOS as XT) 03C3h
 1-0	reserved (0)
SeeAlso: #P0708,#P0749


Bitfields for S3 Trio32/64/64V+ "CR66" Extended Miscellaneous Control 1 reg:
Bit(s)	Description	(Table P0749)
 7	enable PCI bus disconnect on misaligned burst memory accesses
 6	tri-state pixel address bus
---Trio32/64---
 5-0	reserved (0)
---Trio64V+ ---
 5	??? (officially reservd, but set by BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.)
 4	reserved
 3	generate PCI bus disconnect when trying to write to a full FIFO or read
	  from an empty FIFO
	(bit 7 must also be set to enable this feature)
 2	reserved
 1	software reset graphics engine
 0	enable enhanced functions (this is a mirror of
	  PORTIBM PC Portable (uses same BIOS as XT) 4AE8h bit 0)
SeeAlso: #P0708,#P0748,PORTIBM PC Portable (uses same BIOS as XT) 4AE8h


Bitfields for S3 864/964 "CR67" Extended Miscellaneous Control 2 register:
Bit(s)	Description	(Table P0750)
 7-4	color mode???
	(values of 0000/0010/0101/0111 indicate a 16-bit pixel port)
 3-2	???
SeeAlso: #P0708,#P0723,#P0751


Bitfields for S3 Trio32/64/64V+ "CR67" Extended Miscellaneous Control 2 reg:
Bit(s)	Description	(Table P0751)
 7-4	color mode (see #P0688)
 3-2	(Trio32/Trio64) reserved (0)
 3-2	(Trio64V+) streams mode
	00 disable Streams Processor
	01 overlay secondary stream on VGA-mode background
	10 reserved
	11 full Streams Processor operation
 1	reserved (0)
 0	VCLK phase (=0 VCLK is inverted DCLK; =1 VCLK in phase with DCLK)
Note:	the streams mode should only be changed during vertical sync
	  (PORTIBM PC Portable (uses same BIOS as XT) 03DAh bit 3)
SeeAlso: #P0708,#P0750,#P0687


Bitfields for S3 Trio32/64/64V+ "CR68" Configuration 3 register:
Bit(s)	Description	(Table P0752)
 7	(Trio32/64 VL-Bus) Upper Address Decode
	=0 decode all 32 bits of system address bus
	=1 SAUP input used to decode upper address lines
 7	(Trio64V+) memory data bus size
	=0 32 bits
	=1 64 bits (if >= 2M of memory)
 6-4	monitor information (used by S3 bios)
 3	RAS precharge timing (0 = 3.5 MCLKs, 1 = 2.5 MCLKs)
 2	RAS low timing (0 = 4.5 MCLKs, 1 = 3.5 MCLKs)
 1-0	-CAS and -OE stretch, -WE delay
	00 = 6.5ns stretch, 2 units delay
	01 = 5ns stretch, 1 unit delay
	10 = 3.5ns stretch, no delay
	11 = no stretch, no delay
Note:	the default value of this register is latched from external pins at
	  power-up
SeeAlso: #P0708


Bitfields for S3 Trio32/Trio64 "CR69" Extended System Control 3 register:
Bit(s)	Description	(Table P0753)
 7-4	reserved (0)
 3-0	display start address, bits 19-16
SeeAlso: #P0708,#P0754


Bitfields for S3 Trio32/Trio64 "CR6A" Extended System Control 4 register:
Bit(s)	Description	(Table P0754)
 7-6	reserved
 5-0	bits 19-14 of CPU(Central Processing Unit) The microprocessor which executes programs on your computer. base address
Note:	CR31 bit 0 must be set to enable this register
SeeAlso: #P0708,#P0753


Bitfields for S3 Trio64V+ "CR6F" Configuration 4 register:
Bit(s)	Description	(Table P0755)
 7-5	reserved
 4-3	WE# delay (on both rising and falling edges)
	00 three units
	01 two units
	10 one unit
	11 no delay
 2	disable I/O PORTIBM PC Portable (uses same BIOS as XT) mirror of serial port (MMIO FF20h)
	=0 allow access via either MMIO FF20h or port selected by bit 1
 1	serial port address select (only has effect if bit 2 clear)
	=0 mirror MMIO FF20h at PORTIBM PC Portable (uses same BIOS as XT) 00E8h
	=1 mirror MMIO FF20h at PORTIBM PC Portable (uses same BIOS as XT) 00E2h
 0	configure for Trio64-compatible mode instead of LPB mode
 !!! p.19-16
SeeAlso: #P0708,MEM A000h:FF00h"S3"
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 03D4-03D5 - Tseng Labs VIDEO CHIPS - EXTENDED CRT CONTROL REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 03D4h"COLOR VIDEO",PORTIBM PC Portable (uses same BIOS as XT) 03D4h"S3",PORTIBM PC Portable (uses same BIOS as XT) 03D4h"Cirrus"

03D4  RW  CRT control register index (see #P0756)
03D5  RW  CRT control register value


(Table P0756)
Values for Tseng Labs ET3000/ET4000 CRT Controller register index:
 00h-18h same as EGAEnhanced Graphics Adapter(Enhanced Graphics Adapter) IBMInternational Busiuness Machines's second color video board for the IBMInternational Busiuness Machines PCIBM PC family, capable of a maximum resolution of 640x350 pixels in 16 simultaneous colors of a total of 64 possible colors./VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. (see #P0708)
---ET3000 only---
 1Bh	x-zoom start register
	The existence of this register is often used to decide between ET3000
	  and ET4000, as the ET4000 does not offer hardware-zoom features.
 1Ch	x-zoom end register
 1Dh	y-zoom start register low
 1Eh	y-zoom end register low
 1Fh	y-zoom start & end high register
 20h	zoom start address register low
 21h	zoom start address register medium
 23h	extended start address (see register 33h)
 24h	compatibility register (see register 34h)
 25h	overflow high register (see registers 35h, 07h)
---ET4000---
 32h	RAS/CASsee Communicating Applications Specification configuration ('key' protected) (see #P0757)
 33h	extended start address
	      This register is often used to decide between ET4000
	      and ET3000, when bit3-0 can be reread after write.
	       bit7-4 : reserved
	       bit3-2 : cursor address bit 17-16
	       bit1-0 : linear start address bits 17-16
 34h	6845 compatibility control register ('key' protected)
	  (see #P0758)
 35h	overflow high register (protected by 11h, bit7) (see #P0759)
 36h	video system configuration 1 ('key' protected) (see #P0760)
 37h	video system configuration 2 ('key' protected) (see #P0761)
SeeAlso: #P0654,#P0716,#P0717


Bitfields for ET4000 RAS/CASsee Communicating Applications Specification configuration register:
Bit(s)	Description	(Table P0757)
 7	static column memory
	ET4000/W32i: interleave mode
 6	RAL RAS&CASsee Communicating Applications Specification column setup time
 5	RCD RAS & CASsee Communicating Applications Specification time
 4-3	RSP, RAS pre-charge time
 2	CPS, CASsee Communicating Applications Specification pre-charge time
 1-0	CSW, CASsee Communicating Applications Specification low pulse width
SeeAlso: #P0708,#P0758


Bitfields for ET4000 compatibility control register:
Bit(s)	Description	(Table P0758)
 7	6845 compatibility enabled
 6	ENBA enable double scan/underline in AT&TAmerican Telephone and Telegraph mode
 5	ENXL enable translation ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. on writing
 4	ENXR enable translation ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. on reading
 3	ENVS VSE register port address
 2	TRIS tristate ET4000 output pins
 1	CS2 MCLCK clock select 2
 0	EMCK enable translation of CS0 bit
SeeAlso: #P0708,#P0757,#P0759


Bitfields for ET4000 overflow high register:
Bit(s)	Description	(Table P0759)
 7	vertical interlace mode
 6	alternate RMW control
 5	external sync reset (gen-lock) the line/chr counter
 4	line compare bit10
 3	vertical sync start bit10
 2	vertical display end bit10
 1	vertical total bit10
 0	vertical blank start bit10
SeeAlso: #P0708,#P0758,#P0760


Bitfields for ET4000 video system configuration 1 register:
Bit(s)	Description	(Table P0760)
 7	enable 16bit I/O read/write
 6	enable 16bit display memory read/write
 5	addressing mode (0=IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911., 1=TLI)
 4	0=segment / 1=linear system configuration
 3	font width control (1=up to 16bit, 0=8bit)
 2-0	refresh count per line-1
SeeAlso: #P0708,#P0759,#P0761


Bitfields for ET4000 video system configuration 2 register:
Bit(s)	Description	(Table P0761)
 7	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. display memory type (1=VRAM, 0=DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.)
 6	test (1=TLI interal test mode)
 5	priority threshold control (0=more mem BW)
 4	disable block read-ahead
 3	display memory data depth
 2	bus read data latch control
 1-0	display memory data bus width
SeeAlso: #P0708,#P0760