SYSTEM-MANAGEMENT MODE Release 61 Last change 16jul00
Copyright © 1997,1998,1999,2000 Ralf Brown
---------------------------------------------
SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Am486
Format of Am486 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. State-Save Map:
Offset Size Description (Table S0001)
FE00h reserved
FEE4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR3
FEE8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR2
FEECh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR1
FEF0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR0
FEF4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR2
FEF8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. state dump base address
fEFCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. revision ID (see #S0004)
FF00h WORD I/O restart
(set to 00FFh to re-execute trapped I/O)
FF02h WORD halt auto restart
(bit 0 set on entry if SMI during HLT)
(set to 00FFh to restart from HLT)
FF04h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O trap word (see #S0002)
FF08h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. reserved
FF0Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. reserved
FF10h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. previous EIP
FF14h 5 DWORDs ???
FF28h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. reserved
FF2Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. reserved
FF30h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ES limit
FF34h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ES base
FF38h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ES attributes
FF3Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CS limit
FF40h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CS base
FF44h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CS attributes
FF48h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SS limit
FF4Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SS base
FF50h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SS attributes
FF54h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DS limit
FF58h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DS base
FF5Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DS attributes
FF60h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. FS limit
FF64h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. FS base
FF68h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. FS attributes
FF6Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GS limit
FF70h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GS base
FF74h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GS attributes
FF78h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDT limit
FF7Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDT base
FF80h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDT attribute
FF84h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GDT limit
FF88h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GDT base
FF8Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GDT attribute
FF90h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. IDTsee Interrupt Descriptor Table limit
FF94h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. IDTsee Interrupt Descriptor Table base
FF98h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. IDTsee Interrupt Descriptor Table attribute
FF9Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TSS limit
FFA0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TSS base
FFA4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TSS attribute
FFA8h WORD ES
FFAAh WORD unused???
FFACh WORD CS
FFAEh WORD unused???
FFB0h WORD SS
FFB2h WORD unused???
FFB4h WORD DS
FFB6h WORD unused???
FFB8h WORD FS
FFBAh WORD unused???
FFBCh WORD GS
FFBEh WORD unused???
FFC0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDTR
FFC4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TR
FFC8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR7
FFCCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR6
FFD0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EAX
FFD4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ECX
FFD8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EDX
FFDCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EBX
FFE0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ESP
FFE4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EBP
FFE8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ESI
FFECh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EDI
FFF0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EIP
FFF4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EFLAGS
FFF8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR3
FFFCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR0
SeeAlso: #S0003
Bitfields for AMD Am486 I/O trap word:
Bit(s) Description (Table S0002)
31-16 I/O address
15-2 reserved
1 valid I/O instruction
0 direction
SeeAlso: #S0001
---------------------------------------------
SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. AMD-K5
Format of AMD K5 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. State-Save Area:
Offset Size Description (Table S0003)
FE00h reserved
FEF8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. base address
(may be set to any multiple of 32K; initially 00030000h)
FEFCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. revision identifier (see #S0004)
FF00h WORD I/O trap restart slot (see #S0007)
FF02h WORD HLT restart slot (see #S0005)
FF04h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O restart EDI
FF08h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O restart ECX
FF0Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O restart ESI
FF10h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR4
FF14h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR2
FF18h 3 DWORDs reserved
FF24h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ES limit
FF28h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ES base
FF2Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ES attributes
FF30h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CS limit
FF34h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CS base
FF38h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CS attributes
FF3Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SS limit
FF40h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SS base
FF44h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SS attributes
FF48h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DS limit
FF4Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DS base
FF50h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DS attributes
FF54h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. FS limit
FF58h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. FS base
FF5Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. FS attributes
FF60h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GS limit
FF64h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GS base
FF68h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GS attributes
FF6Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDT limit
FF70h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDT base
FF74h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDT attributes
FF78h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TSS limit
FF7Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TSS base
FF80h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TSS attributes
FF84h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GDT limit
FF88h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. GDT base
FF8Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. IDTsee Interrupt Descriptor Table limit
FF90h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. IDTsee Interrupt Descriptor Table base
FF94h 2 DWORDs reserved
FF9Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O trap EIP
FFA0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. reserved
FFA4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. I/O trap DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (see #S0006)
FFA8h WORD ES
FFAAh WORD unused???
FFACh WORD CS
FFAEh WORD unused???
FFB0h WORD SS
FFB2h WORD unused???
FFB4h WORD DS
FFB6h WORD unused???
FFB8h WORD FS
FFBAh WORD unused???
FFBCh WORD GS
FFBEh WORD unused???
FFC0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDTR
FFC4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TR
FFC8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR7
FFCCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR6
FFD0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EAX
FFD4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ECX
FFD8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EDX
FFDCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EBX
FFE0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ESP
FFE4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EBP
FFE8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ESI
FFECh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EDI
FFF0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EIP
FFF4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EFLAGS
FFF8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR3
FFFCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR0
SeeAlso: #S0001
Bitfields for AMD K5 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Revision Identifier:
Bit(s) Description (Table S0004)
31-18 reserved (0)
17 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. base address relocation available (always 1 [enabled] on K5)
16 I/O trap restart supported (always 1 on K5)
15-0 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. revision level (currently 0000h)
SeeAlso: #S0003
Bitfields for AMD K5 Halt Restart Slot:
Bit(s) Description (Table S0005)
15-1 undefined
0 (on SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. entry) entered SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. from Halt state
(at RSM) return to Halt state instead of state in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. state-save area
SeeAlso: #S0003
Bitfields for AMD K5 I/O Trap DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address.:
Bit(s) Description (Table S0006)
31-16 I/O port address
15 I/O was string operation (INS,OUTS,etc.)
14-2 reserved
1 valid I/O instruction
0 direction (0 = output, 1 = input)
SeeAlso: #S0003,#S0007
Bitfields for AMD K5 I/O Trap Restart Slot:
Bit(s) Description (Table S0007)
31-16 reserved
15-0 I/O instruction restart on RSM
0000h resume at next instruction following trapped I/O instruction
(default on SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. entry)
00FFh re-execute the trapped I/O instruction
Note: before changing the restart value, check that the I/O instruction is
actually valid (see #S0006)
SeeAlso: #S0003,#S0006
---------------------------------------------
SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Pentium
Format of Pentium State Dump record:
Offset Size Description (Table S0008)
FE00h 248 BYTEs officially reserved, actually unused
FEF8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. state dump base address (must be multiple of 32K)
FEFCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. revision identifier
bits 15-0: SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. revision level
bit 16: I/O trap extension is present (offset FF00h)
bit 17: SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status. In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. base relocation supported (offset FEF8h)
bits 31-18: reserved
FF00h WORD I/O Trap restart
(set to 00FFh to re-execute trapped I/O)
FF02h WORD Halt auto-restart
(bit 0 set on entry if SMI during HLT; if handler clears it,
the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. returns to the instruction after the interrupted HLT
rather than to the HLT instruction)
FF04h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (undoc) I/O restart EDI / CR0
FF08h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (undoc) I/O restart ECX
FF0Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (undoc) I/O restart ESI
FF10h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (undoc) I/O restart EIP
FF14h 16 BYTEs unused
FF24h WORD (undoc) alternate DR6
FF26h WORD (undoc) RSM control
if bit 0 set on return, the low word of DR6 is loaded from FF26h
instead of FFCCh
FF28h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (undoc) CR4
FF2Ch DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. unused
FF30h 12 BYTEs (undoc) ES descriptor cache
DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. limit
DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. base address
DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. type
FF3Ch 12 BYTEs (undoc) CS descriptor cache
FF48h 12 BYTEs (undoc) SS descriptor cache
FF54h 12 BYTEs (undoc) DS descriptor cache
FF60h 12 BYTEs (undoc) FS descriptor cache
FF6Ch 12 BYTEs (undoc) GS descriptor cache
FF78h 12 BYTEs (undoc) LDT descriptor cache
FF84h 12 BYTEs (undoc) GDT descriptor cache
FF90h 12 BYTEs (undoc) IDTsee Interrupt Descriptor Table descriptor cache
FF9Ch 12 BYTEs (undoc) TSS descriptor cache
FFA8h WORD ES
FFAAh WORD reserved
FFACh WORD CS
FFAEh WORD reserved
FFB0h WORD SS
FFB2h WORD reserved
FFB4h WORD DS
FFB6h WORD reserved
FFB8h WORD FS
FFBAh WORD reserved
FFBCh WORD GS
FFBEh WORD reserved
FFC0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. LDTR
FFC4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. TR
FFC8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR7
FFCCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. DR6
FFD0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EAX
FFD4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ECX
FFD8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EDX
FFDCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EBX
FFE0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ESP
FFE4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EBP
FFE8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. ESI
FFECh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EDI
FFF0h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EIP
FFF4h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. EFLAGS
FFF8h DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR3
FFFCh DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. CR0
SeeAlso: #S0003