RBIL61 - Pentium II

RBIL61 - Pentium II

CALL xxxxh:xxxxh - Plug-and-Play BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v1.0A {#idx160395}{#idx160399}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 30h - Pentium II/III - THERMAL SENSOR {#idx170415}{#idx170450}{#idx170454}{#idx171967}{#idx171971}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 34h - Pentium II/III - THERMAL SENSOR {#idx170419}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. A2h - Pentium Pro/II/III - Processor Information ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. {#idx172434}{#idx172442}{#idx172475}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0000h - Pentium, Pentium Pro - MACHINE CHECK EXCEPTION ADDRESS {#idx165008}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0001h - Pentium, Pentium Pro - MACHINE CHECK EXCEPTION TYPE {#idx165024}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0010h - Pentium, Pentium Pro - TIME STAMP COUNTER REGISTER {#idx165322}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0021h - Pentium II - ??? {#idx165482}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0119h - PentiumII - "BBL_CR_CTL" - CACHE CONTROL REGISTER {#idx165861}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:011Eh - Pentium II - "BBL_CR_CTL3" L2 CACHE CONTROL REGISTER 3 {#idx165890}{#idx165904}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0174h - Pentium II - "SYSENTER_CS" - SYSENTER target CS {#idx165960}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0175h - Pentium II - "SYSENTER_ESP" - SYSENTER target ESP {#idx165968}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0176h - Pentium II - "SYSENTER_EIP" - SYSENTER target EIP {#idx165975}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0186h - Pentium Pro - "EVNTSEL0" - PERFORM. COUNTER EVENT SELECTION 0 {#idx166026}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:040Ch - Pentium II - "MC4_CTL" Machine Check Control 4 {#idx166331}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:040Dh - Pentium II - "MC4_STATUS" Machine Check Status 4 {#idx166337}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:040Eh - Pentium II - "MC4_ADDR" Machine Check Address 4 {#idx166345}

Notes {#idx164989}

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