MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000004h - Pentium - (TR2) INSTRUCTION CACHE END BITS
Size:	4 bits
Access:	Read/Write
Note:	documented as reserved on Pentium MMX
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000002h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000005h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 80000004h


Bitfields for Instruction CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. End Bits (TR2):
Bit(s)	Description	(Table R0003)
 63-4	reserved (0)
 3-0	end bits (each set bit indicates the last byte of an instruction in
	  TR3 during code cache access)
Note:	when a new line is written into the code cache, all end bits are set;
	  the instruction decoder then clears those bits corresponding to
	  bytes which are not the last byte of an instruction
SeeAlso: #R0004
                                                                                

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000004h - Cyrix 6x86MX - TEST ADDRESS
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000003h"Cyrix",MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000005h"Cyrix"


Bitfields for Cyrix 6x86MX Test Address:
Bit(s)	Description	(Table R0063)
 63-32	reserved
 31-0	cache address, like Pentium TR4 (see #R0005)
SeeAlso: #R0062,#R0064