MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000005h - Pentium - (TR3) CACHE DATA TEST REGISTER
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000004h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000006h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 80000005h


Bitfields for CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Data Test Register (TR3):
Bit(s)	Description	(Table R0004)
 63-32	reserved (0)
 31-0	data read/written from/to cache (code or data)
SeeAlso: #R0005,#R0062
                                                                                

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000005h - Cyrix 6x86MX - TEST COMMAND/STATUS
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000004h"Cyrix"


Bitfields for 6x86MX Test Command/Status:
Bit(s)	Description	(Table R0064)
 63-32	reserved
 31-0	command, similar to Pentium TR5 (see #R0006)
 31-24	reserved
 23	"SMI" select SMI memory space
 22-20	reserved
 19	valid data
 18-16	"MESI"
	bits 19-16 together specify state of cache line
	    1000 modified
	    1001 shared
	    1010 exclusive
	    0011 invalid
	    1100 locked valid
	    0111 locked invalid
 15-12	reserved
 11-8	"MRU" used to determine LRU line
 7-6	reserved
 5-4	SET
 3-2	reserved
 1-0	control field
	00 flush cache without invalidation
	01 write cache
	10 read cache
	11 no cache or test register modification
SeeAlso: #R0062,#R0063