MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000006h - Pentium - (TR4) CACHE TAG
Size:	32 bits
Access:	Read/Write
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000005h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000007h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 80000006h


Bitfields for CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Tag Test Register (TR4):
Bit(s)	Description	(Table R0005)
 63-32	reserved (0)
 31-8	cache tag (bits 35-12 of address)
 7-5	reserved (0)
 4-3	reserved (0) (P54C [non-MMX Pentium])
 2	LRU (P54C)
	=0  Way 0
	=1  Way 1
 4-2	LRU (P55C [PentiumMMX])
	=X00  Way 0
	=X10  Way 1
	=0X1  Way 2
	=1X1  Way 3
 1-0	Valid
	---code cache (selected by TR5)---
	x0 cache line invalid
	x1 cache line valid
	---data cache (selected by TR5)---
	00 cache line invalid
	01 cache line shared
	10 cache line exclusive
	11 cache line modified
SeeAlso: #R0004,#R0006,#R0063