MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000000Bh - Pentium, PentiumMMX - (TR9) BRANCH TARGET BUFFER TAG Size: 32 bits Access: Read/Write SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000009h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000000Ch,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000000Bh Bitfields for non-MMX Pentium Branch Target Buffer Tag (TR9): Bit(s) Description (Table R0010) 63-32 reserved (0) 31-6 tag address (bits 31-6 of last byte of branch) 5-2 reserved (0) 1-0 history (state of current branch) SeeAlso: #R0012,#R0013,#R0011 Bitfields for PentiumMMX Branch Target Buffer Tag (TR9): Bit(s) Description (Table R0011) 63-32 reserved 31-8 tag address (bits 31-8 of last byte of branch) 7-6 offset (bits 1-0 of last byte of branch) 5 valid BTB entry 4 branch is predicted as taken 3-0 history (state of current branch) SeeAlso: #R0010