MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000110h - Centaur (IDTsee Interrupt Descriptor Table) C6/WinChip2 - Memory Configuration Register #0 Size: 64 bits Access: Write-Only SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000107h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000111h,MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00000117h"Centaur" Bitfields for Centaur (IDTsee Interrupt Descriptor Table) WinChip C6 Memory Configuration Register: Bit(s) Description (Table R0041) 63-44 base address of memory region 43-32 reserved 31-12 memory region mask (region is hit if (base AND address) == (mask AND address)) 11-5 reserved 4-3 memory write order 00 strong ordering 01 weak for string 10 weak for stack 11 weak ordering for all writes 2 enable write merging for stack writes 1 enable write merging for string writes 0 enable write merging for other writes SeeAlso: #R0045