MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001004h - IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. 486BL3 - PROCESSOR CONTROL REGISTER
Size:	24 bits
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001000h


Bitfields for IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. 486BL3 Processor Control Register:
Bit(s)	Description	(Table R0056)
 63-24	reserved
 23	OS/2 boot (0=DD1 hardware, 1=DD0 hardware)
 22	MOV CR0,x Decode
	0: DD0, DD1A, DD1B, DD1D hardware
	1: DD1C hardware
 21	reserved
 20	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Low Power (DD1 only: cache disabled when not in use)
 19	reserved
 18	NOP timing
	0: 2 cycles on DD0, 3 cycles on DD1
	1: 3 cycles on DD0, 2 cycles on DD1
 17	bus pipelining for 16-bit accesses
 16-5	reserved???
 4	MOVS split
 3	power-saving cache feature
 2	reserved
 1	enable MOV CRx decode
	(reserved on DD1B, DD1C)
 0	reserved
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001000h
                                                                                

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001004h - Pentium Pro - DEBUG REGISTER 4 
SeeAlso: MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001003h"Pro",MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like.	These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 00001005h"Pro"