PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Intel 82358DT 'Mongoose' EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). CHIPSET - 82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. CONTROLLER
Notes:	this chip uses a chip ID of 01
	the LIM register herein use a chip ID of 1A
Index: Intel 82351

0022  -W  index for accesses to data port (see #P0036,#P0037,#P0038)
0023  RW  chip set data


(Table P0035)
Values for Intel 82351/82359 chip ID:
 01h	82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. controller, general registers
 02h	82351 EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). local I/O support
 A1h	82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. controller, EMSsee Expanded Memory Specification registers
 FFh	no chip accessible (default)
SeeAlso: #P0036,#P0037,#P0038


(Table P0036)
Values for 82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. controller general register index:
 00h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bank 0 type
	bit 7	unknown
	bit 6-4	000 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. in bank 0 (standard)
		001 bank 1
		010 bank 2
		011 bank 3
		100 banks 0,1
		101 banks 2,3
		110 banks 0,1,2,3
		111 empty (standard for 1,2,3)
	bit 3-2	unknown
	bit 1-0	00 64K chips used
		01 256K
		10 1M
		11 4M
 01h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bank 1 type
 02h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bank 2 type
 03h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bank 3 type
 04h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. speed detection/selection
 05h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. interleave control
 06h	RAS line mode
 07h	cache-enable selection
 08h	mode register A (DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM., cache)
 09h	mode register B (cache, burst modes, BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. size)
 0Ah	mode register C (concurrency control, burst/cycle speed)
 10h	host timing
 11h	host-system delay timing
 12h	system timing
 13h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. row precharge time
 14h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. row timing
 15h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. column timing
 16h	CASsee Communicating Applications Specification pulse width
 17h	CAS-to-MDS delay
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 28h-2Ch	parity-error trap address
 30h	page hit cycle length (read)
 31h	page miss cycle length (read)
 32h	row miss cycle length (read)
 33h	page hit cycle length (write)
 34h	page miss cycle length (write)
 35h	row miss cycle length (write)
 40h	memory enable 00000h-7FFFFh
 41h	memory enable 80000h-9FFFFh
 42h	memory enable A0000h-AFFFFh
 43h	memory enable B0000h-BFFFFh
 44h	memory enable C0000h-CFFFFh
 45h	memory enable D0000h-DFFFFh
 46h	memory enable E0000h-EFFFFh
 47h	memory enable F0000h-FFFFFh
 4Eh	remap 80000h-FFFFFh to extended memory
 50h-53h	programmable attribute map 1
 54h-57h	programmable attribute map 2
 58h-5Bh	programmable attribute map 3
 5Ch-5Fh	programmable attribute map 4
 83h-84h	split address register (address bits A31-A20)
 85h	cache control
 8Bh	system throttle
 8Ch	host throttle
 8Dh	host memory throttle watchdog
 8Eh	host system throttle
 8Fh	host system throttle watchdog
 90h	RAM(Random Access Memory)	See also DRAM, SRAM. enable
 91h	RAM(Random Access Memory)	See also DRAM, SRAM. disable
 92h-93h	elapsed-time registers
 94h-95h	host memory ownership request
 96h-97h	system memory ownership request
 98h-99h	host memory ownership
 9Ah-9Bh	system bus ownership
 9Ch-9Dh	host system bus request
 9Eh-9Fh	memory ownership transfer
SeeAlso: #P0037,#P0038


(Table P0037)
Values for Intel 82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. controller EMSsee Expanded Memory Specification register index:
 00h	EMSsee Expanded Memory Specification cotnrol
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 80h-8Fh	EMSsee Expanded Memory Specification page registers, pages 0-7
SeeAlso: #P0036,#P0038


(Table P0038)
Values for Intel 82351 EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). Local I/O register index:
 21h	chip ID register -- selects which chip responds on these ports
	(see #P0035)
 C0h	peripheral enable register A
 C1h	peripheral enable register B
 C2h	parallel configuration register
 C3h	serial configuration register A
 C4h	floppy disk controller configuration register
 C5h	serial configuration register B
 C6h	COM3 port address (low)
 C7h	COM3 port address (high)
 C8h	COM4 port address (low)
 C9h	COM4 port address (high)
 D0h-D3h	general chip select lines 0-3 (mask registers)
 D4h-D7h	general chip select line addresses 0-3 (low bytes)
 D8h-DBh	general chip select line addresses 0-3 (high bytes)
 DCh	extended CMOS RAMA small amount (typically 64 or 128 bytes) of memory in the system's real-time clock chip that is preserved by the clock's battery and is used for storing configuration information.  See also Real-Time Clock. page port address (low)
 DDh	extended CMOS RAMA small amount (typically 64 or 128 bytes) of memory in the system's real-time clock chip that is preserved by the clock's battery and is used for storing configuration information.  See also Real-Time Clock. page port address (high)
 DFh	extended CMOS RAMA small amount (typically 64 or 128 bytes) of memory in the system's real-time clock chip that is preserved by the clock's battery and is used for storing configuration information.  See also Real-Time Clock. access select address (high byte)
 E8h-EBh	EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). ID configuration registers (reflect at PORTIBM PC Portable (uses same BIOS as XT) 0C80h)
SeeAlso: #P0036,#P0037
                                                                                

PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Intel 82374EB/SB EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). CHIPSET
Index: Intel 82374EB;Intel 82374SB

0022  -W  index for accesses to data port (see #P0039)
0023  RW  chip set data


!!!29047604.pdf pg. 36
(Table P0039)
Values for Intel 82374 register index:
 02h	ESC identification register
	(82374 will only respond to ports 0022h and 0023h after an 0Fh
	 is written to this register)
 08h	revision ID register
 40h	mode select (see #P0040)
 42h	BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Chip Select A (see #P0041)
 43h	BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Chip Select B (see #P0042)
 4Dh	EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). clock divisor (see #P0043)
 4Eh	peripheral Chip Select A (see #P0044)
 4Fh	peripheral Chip Select B (see #P0045)
 50h-53h EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). ID registers
 57h	scatter/gather relocate base address (see also #01075)
	(specifies bits 15-0 if S/G port addresses [low byte always 10h-3Fh])
 59h	APIC base address relocation
 60h-63h PCI IRQn# route control (see also #01076)
 64h	general-purpose chip select low address 0
 65h	general-purpose chip select high address 0
 66h	general-purpose chip select mask register 0
 68h	general-purpose chip select low address 1
 69h	general-purpose chip select high address 1
 6Ah	general-purpose chip select mask register 1
 6Ch	general-purpose chip select low address 2
 6Dh	general-purpose chip select high address 2
 6Eh	general-purpose chip select mask register 2
 6Fh	general-purpose peripheral X-Bus control
---SB only---
 70h	PCI/APIC control (see #P0046)
 88h	test control
 A0h	SMI control (see #P0047)
 A2h-A3h  SMI enable (see #P0048)
 A4h-A7h  System Event Enable (see #P0049)
 A8h	Fast-Off timer
 AAh-ABh SMI Request (see #P0050)
 ACh	Clock Scale STPCLK# low timer
 AEh	Clock Scale STPCLK# high timer


Bitfields for 82374EB mode select (register 40h):
Bit(s)	Description	(Table P0040)
  7	reserved
  6	enable the selected (MREQ[7:4]#/PIRQ[3:0]# functionality
  5	enable/disable configuration RAM(Random Access Memory)	See also DRAM, SRAM. Page Address (CPG[4:0]) generation
	=1 accesses to the configuration RAM(Random Access Memory)	See also DRAM, SRAM. space will generate the RAM(Random Access Memory)	See also DRAM, SRAM. page
	  address on the LA[31:27]# pins (default)
	=0 the CPG[4:0] signals will not be activated
  4	General Purpose Chip Selects: select GPCS[2:0]#/ECS[2:0] pins' function
	=0 GPCS[2:0]# functionality is selected
	=1 ESC[2:0] functionality is selected
  3	System Error: enable generation of NMIsee Non-Maskable Interrupt based on SERR# signal pulsing
	=0 NMIsee Non-Maskable Interrupt is negated and SERR# is disabled from generating an NMIsee Non-Maskable Interrupt
	=1 NMIsee Non-Maskable Interrupt signal is asserted when NMIs are enabled via the NMIERTC
	  Register and SERR# is asserted
	Note: other NMIsee Non-Maskable Interrupt sources are enabled/disabled via the NMISC register
  2-0	PIRQx Mux/Mapping Control: select muxing/mapping of PIRQ[3:0]# with
	  MREQ[7:4] and group of X-Bus signals (DLIGHT#, RTCWR#, RTCRD#).
	Different bit combinations select the number of EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). slots or group of
	  X-Bus signals which can be supported with the certain number of
	  PIRQx# signals by determining the functionality of pins
	  AEN[4:1]/EAEN[4:1], MACK[3:0]#/EMACK[3:0]#, MREQ[7:4]/PIRQ[3:0]#,
	  DLIGHT#/PIRQ0#, FDCCS#/PIRQ1#, RTCWR#/PIRQ2#, and RTCRD#/PIRQ3#.
SeeAlso: #P0039


Bitfields for 82374EB BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Chip Select A "BIOSCSA" (register 42h):
Bit(s)	Description	(Table P0041)
  7-6	reserved
  5	Enlarged BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.: assert LBIOSCS# for memory read cycles to locations
	  FFF80000h-FFFDFFFFh
  4	High BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.: assert LBIOSCS# for memory read cycles to locations
	  0F0000h-0FFFFFh, FF0000h-FFFFFFh, and FFFF0000h-FFFFFFFFh
  3	Low BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. 4: assert LBIOSCS# for memory read cycles to locations
	  0EC000h-0EFFFFh, FFEEC000h-FFEEFFFFh, and FFFEC000h-FFFEFFFFh
  2	Low BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. 3: assert LBIOSCS# for memory read cycles to locations
	  0E8000h-0EBFFFh, FFEE8000h-FFEEBFFFh, and FFFE8000h-FFFEBFFFh
  1	Low BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. 2: assert LBIOSCS# for memory read cycles to locations
	  0E4000h-0E7FFFh, FFEE4000h-FFEE7FFFh, and FFFE4000h-FFFE7FFFh
  0	Low BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. 1: assert LBIOSCS# for memory read cycles to locations
	  0E0000h-0E3FFFh, FFEE0000h-FFEE3FFFh, and FFFE0000h-FFFE3FFFh
Note:	if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be
	  asserted for write cycles as well as read cycles on any enabled range
SeeAlso: #P0039,#P0042


Bitfields for 82374EB BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Chip Select B (register 43h):
Bit(s)	Description	(Table P0042)
  7-4	Reserved
  3	BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. Write Enable: assert LBIOSCS# for both memory read AND write
	  cycles for addresses in the decoded and enabled BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. range
	  (see #P0041)
  2	16 Meg BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.: assert LBIOSCS# for memory read cycles to locations
	  FF0000h-FFFFFFh
  1	High VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.: assert LBIOSCS# for memory read cycles to locations
	  0C4000h-0C7FFFh
  0	Low VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers. BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.: assert LBIOSCS# for memory read cycles to locations
	  0C0000h-0C3FFFh
Note:	if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be
	  asserted for write cycles as well as read cycles on any enabled range
	  above
SeeAlso: #P0039,#P0041


Bitfields for 82374EB EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). clock divisor (register 4Dh):
Bit(s)	Description	(Table P0043)
  7-6	Reserved
  5	Co-processor Error: specify if the FERR# signal is connected to the
	  ESC internal IRQ13 interrupt signal.
	=0 FERR# signal is ignored by the ESC (i.e. this signal is not
	  connected to any logic in the ESC).
	=1 assert IRQ13 to the interrupt controller if FERR# signal is asserted
  4	82374EB: Reserved
	82374SB: ABFULL (with IRQ12):
	=0 internal IRQ12 is directed to the interrupt controller and 
	  transitions on ABFULL have no effect on this interrupt signal
	=1 the assertion of ABFULL is latched and directed to the internal
	  IRQ12 signal in the following manner:
	    If the interrupt controller is programmed for edge detect mode on
	      IRQ12, a low-to-high transition is generated on the internal
	      IRQ12 signal. Transitions on the IRQ12 input pin are not
	      reflected on the internal IRQ12 signal.
	    If the interrupt controller is programmed for level-sensitive mode,
	      a high-to-low transition is generated on the internal IRQ12
	      signal.  Transitions on the IRQ12 input pin are also reflected
	      on the internal IRQ12 signal.
	The latching of the ABFULL signal is cleared by an I/O read of
	  address 60h (no aliasing) or by a hard reset.
  3	82374EB: Reserved
	82374SB: Keyboard Full (KBFULL): select edge-detect KBFULL function on
	  the IRQ1 input signal
	=0 IRQ1 is directed to the interrupt controller
	=1 (default) IRQ1 is latched and directed to the interrupt controller.
	  The latched IRQ1 is cleared by an I/O read of address 60h (no
	  aliasing) or by a hard reset.
  2-0	Clock Divisor: select the integer used to divide the PCICLK down to
	  generate the BCLK.
	000 4 (33.33 MHz) 8.33 MHz (default after reset)
	001 3 (25 MHz) 8.33 MHz
	01x reserved
	1xx reserved
SeeAlso: #P0039


Bitfields for 82374EB peripheral Chip Select A (register 4Eh):
Bit(s)	Description	(Table P0044)
  7	Reserved
  6	Keyboard Controller Mapping
	=0 the keyboard controller encoded chip select signal and the X-Bus
	  transceiver enable (XBUSOE#) are generated for accesses to address
	  locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB) and
	  66h (82374EB only).
	=1 the keyboard controller chip select signals are generated for
	  accesses to the above address locations. However XBUSOE# is disabled.
	Note:	bit 1 must be 1 for either value of this configuration bit to
		  decode an access to locations 60h, 62h, 64h, or 66h.
  5	Floppy Disk/IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. Controller Address range
	=0 primary (1Fxh and 3Fxh)
	=1 secondary (17xh and 37xh)
  4	IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. DECODE: enable or disable IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. locations 1F0h-1F7h (primary) or
	  170h-177h (secondary) and 3F6h,3F7h (primary) or 376h,377h (sec).
	82374EB: When this bit is set to 0, the IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. encoded chip select signals
	  and the X-Bus transceiver signal (XBUSOE#) are not generated for
	  these addresses.
	82374SB: When this bit is set to 0, the IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. encoded chip select signals
	  and the X-Bus transceiver signal (XBUSOE#) are not generated for
	  addresses 1F0h-1F7h (primary) or 170h-177h (secondary) and 3F6h or
	  376h.	 Read/write accesses to addresses 377h and 3F7h are not
	  disabled and still generate XBUSOE#.
  3-2	Floppy Disk and IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI./Floppy Disk Decodes: Bits 2 and 3 are used to
	  enable or disable the floppy locations as indicated. Bit 2 defaults
	  to enabled (1) and bit 3 defaults to disabled (0) when a reset occurs
  1	Keyboard Controller Decode: enable the keyboard controller address
	  locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB), and
	  66h (82374EB only).
	=0 the keyboard controller encoded chip select signals and the X-Bus
	  transceiver signal (XBUSOE#) are not generated for these locations
	Note:	the value of this bit affects control function (keyboard
		  controlling mapping) provided by bit 6 of this register.
  0	Real Time Clock Decode: enable the RTCsee Real-Time Clock address locations 70h-77h.
	=0 the RTCsee Real-Time Clock encoded chip	select signals RTCALE, RTCRD, RTCWR#, and
	  XBUSOE# signals are not generated for these addresses.
SeeAlso: #P0039,#P0045


Bitfields for 82374EB peripheral Chip Select B (register 4Fh):
Bit(s)	Description	(Table P0045)
  7	CRAM Decode: enable I/O write accesses to location 0C00h and I/O
	  read/write accesses to locations 0800h-08FFh. The configuration RAM(Random Access Memory)	See also DRAM, SRAM.
	  read and write (CRAMRD#, CRAMWR#) strobes are valid for accesses to
	  0800h-08FFh.
  6	Port 92 Decode: enable access to Port 92 (default at PCIRST is enabled)
  5-4	select which Parallel Port address range (LPT1, 2, or 3) is decoded.
	00 LPT1 (3BCh-3BFh)
	01 LPT2 (378h-37Fh)
	10 LPT3 (278h-27Fh)
	11 disabled
  3-2	Serial Port B Address Decode: If either COM1 or COM2 address ranges
	  are selected, these bits default to disabled upon PCIRST.
	00 3F8h-3FFh (COM1)
	01 2F8h-2FFh (COM2)
	10 Reserved
	11 Port B disabled
  1-0	Serial Port A Address Decode: If either COM1 or COM2 address ranges are
	  selected, these bits default to disabled upon PCIRST.
	00 3F8h-3FFh (COM1)
	01 2F8h-2FFh (COM2)
	10 Reserved
	11 Port A disabled
SeeAlso: #P0039,#P0044


Bitfields for 82374SB PCI/APIC control (register 70h):
Bit(s)	Description	(Table P0046)
  7-2	Reserved
  1	SMI Routing Control (SMIRC)
	=1 SMI is routed via the APIC
	=0 SMI is routed via the SMI# signal
	Note:	when SMRCe1, INTR can not be routed through the APIC, since it
		  is sharing the APIC interrupt input with SMI#.
  0	INTR Routing Control (INTRC): When APIC is enabled (in mixed or pure
	  APIC mode), this bit allows the ESC's external INTR signal to be
	  masked (forces INTR to the inactive state but does not tri-states
	  the signal). Thus, the CPU(Central Processing Unit) The microprocessor which executes programs on your computer.'s INTR pin can be used (by providing a
	  simple -gate) for the APIC Local Interrupt (LINTRx). However, INTR
	  must not be masked via this bit when APIC is disabled and INTR is
	  the only mechanism to signal the 8259 recognized interrupts to the
	  CPU(Central Processing Unit) The microprocessor which executes programs on your computer..
	=1 INTR is disabled (APIC must be enabled)
	=0 INTR is enabled
SeeAlso: #P0039


Bitfields for 82374SB SMI control (register A0h):
Bit(s)	Description	(Table P0047)
  7	reserved (0)
  6-4	reserved
  3	Fast Off Timer Freeze (CTMRFRZ): disable the Fast Off Timer
	Disabling the timer prevents time-outs from occurring while executing
	  SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. code.
  2	STPCLK# Scaling Enable (CSTPCLKSC)
	=0 (default) scaling control of the STPCLK# signal is disabled.
	=1, the STPCLK# signal scaling control is enabled. When enabled (and
	  bit 1=1, enabling the STPCLK# signal), the high and low times for the
	  STPCLK# signal are controlled by the Clock Scaling STPCLK# High Timer
	  and Clock Scaling STPCLK# Low Timer Registers, respectively.
  1	STPCLK# Signal Enable (CSTPCLKE): permits software to place the CPU(Central Processing Unit) The microprocessor which executes programs on your computer.
	  into a low power state.
	=0 (default) STPCLK# signal is disabled and is negated (high)
	=1 the STPCLK# signal is enabled and a read from the APMC Register
	  causes STPCLK# to be asserted
	Software can set this bit to 0 by writing a 0 to it or by any write to
	  the APMC Register.
  0	SMI# Gate (CSMIGATE)
	=0 (default) the SMI# signal is masked and negated
	=1 SMI# signal is enabled and a system management interrupt condition
	  causes the SMI# signal to be asserted
Note:	bit 0 only affects the SMI# signal and does not affect the
	  detection/recording of SMI events (i.e., it does not affect the SMI
	  status bits in the SMIREQ Register). Thus, SMI conditions can be
	  pending when bit 0 is set to 1; if an SMI is already pending, the
	  SMI# signal is asserted.
SeeAlso: #P0039


Bitfields for 82374SB SMI enable (register A2h-A3h):
Bit(s)	Description	(Table P0048)
  15-8	Reserved
  7	APMC Write SMI Enable
	=0 writes to the APMC Register do not generate an SMI
	=1 writes to the APMC Register generate an SMI
  6	EXTSMI# SMI Enable
	=1 asserting the EXTSMI# input signal generates an SMI
  5	Fast Off Timer SMI Enable
	=1 Fast-Off timer generates an SMI when it decrements to zero
  4	IRQ12 SMI Enable (PS/2IBM PS/2, any model Mouse Interrupt)
	=1 asserting the IRQ12 input signal generates an SMI
  3	IRQ8 SMI Enable (RTCsee Real-Time Clock Alarm Interrupt)
	=1 asserting the IRQ8 input signal generates an SMI
  2	IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse)
	=1 asserting the IRQ3 input signal generates an SMI
  1	IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse)
	=1 asserting the IRQ3 input signal generates an SMI
  0	IRQ1 SMI Enable (Keyboard Interrupt)
	=1 asserting the IRQ1 input signal generates an SMI
SeeAlso: #P0039


Bitfields for 82374SB System Event Enable (register A4h-A7h):
Bit(s)	Description	(Table P0049)
  31	Fast Off SMI Enable (FSMIEN)
	=1 an SMI causes a system event that re-loads the Fast Off Timer and a
	  break event that negates the STPCLK# signal
	=0 an SMI does not re-load the Fast Off Timer or negate the STPCLK#
	  signal
  30	reserved
  29	Fast Off NMIsee Non-Maskable Interrupt Enable (FNMIEN)
	=1 an NMIsee Non-Maskable Interrupt (e.g., parity error) causes a system event that re-loads the
	  Fast Off Timer and a break event that negates the STPCLK# signal
	=0 an SMI does not re-load the Fast Off Timer or negate	the STPCLK#
	  signal.
  28-16 reserved
  15-3	These bits are used to prevent the system from entering Fast Off and
	  break any current powerdown state when the selected hardware
	  interrupt (IRQ15-IRQ3) occurs
	=1 the corresponding interrupt causes a	system event that re-loads the
	  Fast Off Timer and a break event that	negates the STPCLK# signal
	=0 the corresponding interrupt does not re-load the Fast Off Timer or
	  negate the STPCLK# signal
  2	reserved
  1-0	These bits are used to prevent the system from entering Fast Off and
	  break any current powerdown state when the selected hardware
	  interrupt (IRQ1-IRQ0) occurs
	=1 the corresponding interrupt causes a	system event that re-loads the
	  Fast Off Timer and a break event that	negates the STPCLK# signal
	=0 the corresponding interrupt does not re-load the Fast Off Timer or
	  negate the STPCLK# signal
SeeAlso: #P0039


Bitfields for 82374SB SMI Request (register AAh-ABh):
Bit(s)	Description	(Table P0050)
  15-8	Reserved
  7	APM SMI Status (RAPMC): set to 1 to indicate that a write to the APM
	  Control Register caused an SMI
  6	EXTSMI# SMI Status (REXT): set to 1 when EXTSMI# caused an SMI
  5	Fast Off Timer Expired Status (RFOT): set to 1 to indicate that the
	  Fast Off Timer expired and caused an SMI.  The Fast Off  timer
	  re-starts counting on the next clock after it expires.
  4	SMI caused by IRQ12
  3	SMI caused by IRQ8
  2	SMI caused by IRQ4
  1	SMI caused by IRQ3
  0	SMI caused by IRQ1
SeeAlso: #P0039