PORTIBM PC Portable (uses same BIOS as XT) 04D0-04D1 - EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. control
Note:	these registers are also supported on many non-EISA machines, e.g. by
	  most machines using Intel PCI chipsets
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 04D4h-040Bh"EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus)."

04D0  -W  IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 0-7 interrupt edge/level registers (see #P0891)
04D1  -W  IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 8-15 interrupt edge/level registers (see #P0892)


Bitfields for EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 0-7 interrupt edge/level register:
Bit(s)	Description	(Table P0891)
 7	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 7 is level sensitive
 6	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 6 is level sensitive
 5	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 5 is level sensitive
 4	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 4 is level sensitive
 3	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 3 is level sensitive
 2-0	reserved
SeeAlso: #P0892


Bitfields for EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 8-15 interrupt edge/level register:
Bit(s)	Description	(Table P0892)
 7	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 15 is level sensitive
 6	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 14 is level sensitive
 5	reserved (1)
 4	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 12 is level sensitive
 3	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 11 is level sensitive
 2	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 10 is level sensitive
 1	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. 9  is level sensitive
 0	reserved
SeeAlso: #P0891