PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - CHIP SET DATA
Note:	These two ports are used by numerous chipsets.	Various chipsets are
	  detailed below.

0022  -W  index for accesses to data port
0023  RW  chip set data
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"5x86",PORTIBM PC Portable (uses same BIOS as XT) 0022h"6x86"

0022  -W  index for accesses to next port (see #P0017)
0023  RW  cache configuration register array (indexed by PORTIBM PC Portable (uses same BIOS as XT) 0022h)
	Note:	the index must be written to PORTIBM PC Portable (uses same BIOS as XT) 0022h before every access
		  to PORTIBM PC Portable (uses same BIOS as XT) 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles


(Table P0017)
Values for Cyrix Cx486SLC/DLC CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Configuration register number:
 C0h	CR0 (see #P0019)
 C1h	CR1 (see #P0020)
 C4h	non-cacheable region 1, start address bits 31-24
 C5h	non-cacheable region 1, start address bits 23-16
 C6h	non-cacheable region 1, start addr 15-12, size (low nibble) (see #P0018)
 C7h	non-cacheable region 2, start address bits 31-24
 C8h	non-cacheable region 2, start address bits 23-16
 C9h	non-cacheable region 2, start addr 15-12, size (low nibble) (see #P0018)
 CAh	non-cacheable region 3, start address bits 31-24
 CBh	non-cacheable region 3, start address bits 23-16
 CCh	non-cacheable region 3, start addr 15-12, size (low nibble) (see #P0018)
 CDh	non-cacheable region 4, start address bits 31-24
 CEh	non-cacheable region 4, start address bits 23-16
 CFh	non-cacheable region 4, start addr 15-12, size (low nibble) (see #P0018)
SeeAlso: #P0023,#P0021


(Table P0018)
Values for Cyrix Cx486SLC/DLC non-cacheable region sizes:
 00h	disabled
 01h	4K
 02h	8K
 03h	16K
 04h	32K
 05h	64K
 06h	128K
 07h	256K
 08h	512K
 09h	1M
 0Ah	2M
 0Bh	4M
 0Ch	8M
 0Dh	16M
 0Eh	32M
 0Fh	4G
SeeAlso: #P0017


Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0:
Bit(s)	Description	(Table P0019)
 0	"NC0" first 64K of each 1M noncacheable in real/V86see Virtual-86 Mode
 1	"NC1" 640K-1M noncacheable
 2	"A20M" enables A20M# input pin
 3	"KEN"  enables KEN# input pin
 4	"FLUSH" enables FLUSH input pin
 5	"BARB" enables internal cache flushing on bus holds
 6	"C0" cache direct-mapped instead of 2-way associative
 7	"SUSPEND" enables SUSP# input and SUSPA# output pins
SeeAlso: #P0017,#P0020,#P0032


Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1:
Bit(s)	Description	(Table P0020)
 0	"RPL" enables output pins RPLSET and RPLVAL#
SeeAlso: #P0017,#P0019,#P0024
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"Cx486SLC",PORTIBM PC Portable (uses same BIOS as XT) 0022h"5x86",PORTIBM PC Portable (uses same BIOS as XT) 0022h"6x86"

0022  -W  index for accesses to next port (see #P0021)
0023  RW  cache configuration register array (indexed by PORTIBM PC Portable (uses same BIOS as XT) 0022h)
	Note:	the index must be written to PORTIBM PC Portable (uses same BIOS as XT) 0022h before every access
		  to PORTIBM PC Portable (uses same BIOS as XT) 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles


(Table P0021)
Values for Cyrix 486S2/D2/DX/DX2/DX4 configuration register number:
 C2h	CR2 (see #P0025)
 C3h	CR3 (see #P0026)
 CDh	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. region, start address bits 31-24
 CEh	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. region, start address bits 23-16
 CFh	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. region, start addr 15-12, size (low nibble) (see #P0018)
 FEh R	Device Identification #0 (see #P0022)
	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023,#P0031


(Table P0022)
Values for Cyrix device identification:
(#0 /#1)
 00h	Cx486SLC
 01h	Cx486DlC
 02h	Cx486SLC2
 03h	Cx486DLC2
 04h	Cx486SRx
 05h	Cx486DRx
 06h	Cx486SRx2
 07h	Cx486DRx2
 10h	Cx486S (B-step)
 11h	Cx486S2 (B-step)
 12h	Cx486Se (B-step)
 13h	Cx486S2e (B-step)
1Ah/05h	Cx486DX-40
1Bh/08h	Cx486DX2-50
1Bh/0Bh	Cx486DX2-66
1Bh/31h	Cx486DX2-v80
1Fh/36h	Cx486DX4-v100
 28h	5x86 1xs
 29h	5x86 2xs
 2Ah	5x86 1xp
 2Bh	5x86 2xp
 2Ch	5x86 4xs
 2Dh	5x86 3xs
 2Eh	5x86 4xp
 2Fh	5x86 3xp
 30h	6x86 1xs
 31h	6x86 2xs
 32h	6x86 1xp
 33h	6x86 2xp
 34h	6x86 4xs
 35h	6x86 3xs
 36h	6x86 4xp
 37h	6x86 3xp
Note:	#0 is the value in configuration register FEh, while #1 is the value
	  in configuration register FFh
SeeAlso: #P0021
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"Cx486SLC",PORTIBM PC Portable (uses same BIOS as XT) 0022h"486S2",PORTIBM PC Portable (uses same BIOS as XT) 0022h"6x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORTIBM PC Portable (uses same BIOS as XT) 0022h)
	Note:	the index must be written to PORTIBM PC Portable (uses same BIOS as XT) 0022h before every access
		  to PORTIBM PC Portable (uses same BIOS as XT) 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles


(Table P0023)
Values for Cyrix 5x86 configuration registers:
 20h	Performance Control (see #P0028)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 CDh	System Memory Management address region #0 (smar0) (see #P0029)
 CEh	System Memory Management address region #1 (smar1)
 CFh	System Memory Management address region #2 (smar2)
 E8h	Configuration Control Register 4
 F0h	Power Management (see #P0030)
 FEh R	Device Identification #0 (see #P0022)
	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0021,#P0031


Bitfields for Cyrix 5x86,6x86 Configuration Control Register 1 (CCR1):
Bit(s)	Description	(Table P0024)
 0	reserved
 1	enable SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. pins
 2	system management memory access
 3	main memory access
 4	(6x86) no LOCK during bus cycles
 6-5	reserved
 7	(6x86) use address region 3 as SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. space
Note:	bits 1,2,7 may only be written when CCR3 bit 0 is enabled
SeeAlso: #P0020,#P0025,#P0026,#P0027


Bitfields for Cyrix 5x86,6x86 Configuration Control Register 2 (CCR2):
Bit(s)	Description	(Table P0025)
 0	reserved
 1	enable write-back cache interface pins
 2	lock NW bit
 3	suspend on HLT instruction
 4	write-through region 1
 5	reserved
 6	enable burst write cycles
 7	enable suspend pins
SeeAlso: #P0024,#P0026,#P0027


Bitfields for Cyrix 5x86,6x86 Configuration Control Register 3 (CCR3):
Bit(s)	Description	(Table P0026)
 0	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. register lock (can only be cleared in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. mode or by CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reset)
 1	NMIsee Non-Maskable Interrupt enable
 2	linear address burst cycles (5x86,6x86 only)
	=0 Pentium-compatible
	=1 linear sequencing
 3	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. mode (5x86 only)
	=0 486SL
	=1 Cyrix
 7-4	map enable (5x86,6x86 only)
	0000 only allow access to configuration registers C0h-CFh,FEh,FFh
	0001 enable access to all configuration registers
SeeAlso: #P0024,#P0025,#P0027,#P0028,#P0030


Bitfields for Cyrix 5x86,6x86 Configuration Control Register 4 (CCR4):
Bit(s)	Description	(Table P0027)
 2-0	I/O recovery time (000 = none, else 2^N clocks)
 3	enable memory-read bypassing (5x86 only)
 4	enable directory table entry cache
 6-5	reserved
 7	enable CPUID instruction (stepping 1+ and Cx6x86)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0024,#P0025,#P0026


Bitfields for Cyrix 5x86 Performance Control register:
Bit(s)	Description	(Table P0028)
 0	return stack enabled (speculatively execute code after current CALL)
 1	branch-target buffer enabled
 2	loop enable
 6-3	reserved (0)
 7	load-store serialization enabled
	(memory reads and writes may be reorganized into optimum order)
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
SeeAlso: #P0030,#P0024


Bitfields for Cyrix 5x86 SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. Address Region register:
Bit(s)	Description	(Table P0029)
 3-0	block size
 23-4	starting address


Bitfields for Cyrix 5x86 Power Management register:
Bit(s)	Description	(Table P0030)
 1-0	core clock to bus clock ratio
	00 1:1
	01 2:1
	10 reserved
	11 3:1
 2	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. running at half bus speed, ignore bits 1-0
Note:	this register is only accessible when bits 7-4 of CCR3 are 0001
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"Cx486",PORTIBM PC Portable (uses same BIOS as XT) 0022h"5x86"

0022  -W  index for accesses to next port (see #P0023)
0023  RW  configuration control register array (indexed by PORTIBM PC Portable (uses same BIOS as XT) 0022h)
	Note:	the index must be written to PORTIBM PC Portable (uses same BIOS as XT) 0022h before every access
		  to PORTIBM PC Portable (uses same BIOS as XT) 0023h; out-of-sequence accesses or index values
		  not supported by the processor generate external I/O cycles


(Table P0031)
Values for Cyrix 6x86 configuration registers:
 C0h	Configuration Control Register 0 (CCR0) (see #P0032)
 C1h	Configuration Control #1 (CCR1) (see #P0024)
 C2h	Configuration Control #2 (CCR2) (see #P0025)
 C3h	Configuration Control #3 (CCR3) (see #P0026)
 C4h	Address region 0 (bits 31-24)
 C5h	Address region 0 (bits 23-16)
 C6h	Address region 0 (bits 15-12 and size)
 C7h	Address region 1 (bits 31-24)
 C8h	Address region 1 (bits 23-16)
 C9h	Address region 1 (bits 15-12 and size)
 CAh	Address region 2 (bits 31-24)
 CBh	Address region 2 (bits 23-16)
 CCh	Address region 2 (bits 15-12 and size)
 CDh	Address region 3 (bits 31-24)
 CEh	Address region 3 (bits 23-16)
 CFh	Address region 3 (bits 15-12 and size)
 D0h	Address region 4 (bits 31-24)
 D1h	Address region 4 (bits 23-16)
 D2h	Address region 4 (bits 15-12 and size)
 D3h	Address region 5 (bits 31-24)
 D4h	Address region 5 (bits 23-16)
 D5h	Address region 5 (bits 15-12 and size)
 D6h	Address region 6 (bits 31-24)
 D7h	Address region 6 (bits 23-16)
 D8h	Address region 6 (bits 15-12 and size)
 D9h	Address region 7 (bits 31-24)
 DAh	Address region 7 (bits 23-16)
 DBh	Address region 7 (bits 15-12 and size)
 DCh	Region Control 0
 DDh	Region Control 1
 DEh	Region Control 2
 DFh	Region Control 3
 E0h	Region Control 4
 E1h	Region Control 5
 E2h	Region Control 6
 E3h	Region Control 7
 E8h	Configuration Control Register 4 (see #P0027)
 E9h	Configuration Control Register 5 (see #P0033)
 FEh R	Device Identification #0 (see #P0022)
	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. device ID
 FFh R	Device Identification #1
	bits 3-0: revision
	bits 7-4: stepping
SeeAlso: #P0017,#P0023


Bitfields for Cyrix 6x86 Configuration Control Register 0:
Bit(s)	Description	(Table P0032)
 7-2	???
 1	address region 640K-1M is noncacheable
 0	???
SeeAlso: #P0019


Bitfields for Cyrix 6x86 Configuration Control Register 5:
Bit(s)	Description	(Table P0033)
 7-6	reserved
 5	enable all address-region registers (control registers C4h-DBh)
 4	assert LBA# pin on all accesses to 640K-1M
 3-1	reserved
 0	allocate new cache lines only on read misses
SeeAlso: #P0032,#P0027,#P0031
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - GoldStar 286 - CHIP SET CONFIGURATION REGISTERS
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"Cx486SLC",PORTIBM PC Portable (uses same BIOS as XT) 0022h"486S2",PORTIBM PC Portable (uses same BIOS as XT) 0022h"6x86"

0022  -W  index for accesses to next port (see #P0034)
0023  RW  configuration control register array (indexed by PORTIBM PC Portable (uses same BIOS as XT) 0022h)


(Table P0034)
Values for GoldStar 286 chipset configuration register index:
 60h	turbo control
	write 00h to PORTIBM PC Portable (uses same BIOS as XT) 0023h to turn on turbo, 10h to turn it off
                                                                                

PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP)

0022  RW  chip set data
0023  ?W  index for accesses to data port (see #P0051)


(Table P0051)
Values for Etec Cheetah ET6000 chip set register index:
 10h	system configuration register (see #P0052)
 11h	cache configuration & non-cacheable block size register (see #P0053)
 12h	non-cacheable block address register
	bit 7-1	non-cacheable address, A25-A19
	bit 0	reserved
 13h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bank & type configuration register (see #P0054)
 14h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register (see #P0055)
 15h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. configuration register (see #P0056)


Bitfields for Etec Cheetah ET6000 system configuration register:
Bit(s)	Description	(Table P0052)
 7-6	00 turbo/non-turbo
	01 local device supported
	10 suspend mode
	11 illegal
 5	reserved
 4	refresh selection
	0 = ATIBM PC AT type refresh
	1 = concurrent refresh
 3	slow refresh  95mSec enabled
 2	fast reset delay
	0 = do not use delay
	1 = wait for 2mSec delay
 1	wait for HALT after KBDRST
 0	RAM(Random Access Memory)	See also DRAM, SRAM. at A0000-BFFFF
	0 = ATIBM PC AT bus cycle
	1 = local bus cycle
SeeAlso: #P0051


Bitfields for Etec Cheetah ET6000 cache configuration register:
Bit(s)	Description	(Table P0053)
 7-5	000 disabled
	001 512K
	010 1M
	011 2M
	100 4M
	101 8M
	110 16M
	111 32M
 4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. banks
	0 = 2-bank DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	1 = 4-bank DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
 3-0	reserved
SeeAlso: #P0051


Bitfields for Etec Cheetah ET6000 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bank & type configuration register:
Bit(s)	Description	(Table P0054)
 7-6	bank 3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
	00 none
	01 256K
	10 1M
	11 4M
 5-4	bank 2 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
 3-2	bank 1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
 1-0	bank 0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
SeeAlso: #P0051


Bitfields for Etec Cheetah ET6000 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register:
Bit(s)	Description	(Table P0055)
 7	on-board memory range 15M to 16M disabled
 6	on-board memory range 512K-640K disabled
 5	ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. chip select at C0000-DFFFF enabled
 4	RAS to CASsee Communicating Applications Specification time
	0 = 1 SYSCLCK,	not for R0WS
	1 = 2 SYSCLCK
 3	RAS precharge time
	0 = 1.5 SYSCLCK
	1 = 2.5 SYSCLCK
 2-1	read cycle wait state
	00 = 0 wait state
	01 = 1 ws
	10 = 2 ws
	11 = 3 ws
 0	write cycle wait state
	0 = 0 ws
	1 = 1 ws
SeeAlso: #P0051


Bitfields for Etec Cheetah ET6000 shadow RAM(Random Access Memory)	See also DRAM, SRAM. configuration register:
Bit(s)	Description	(Table P0056)
 7	shadow at C0000-FFFFF
	0 = non-cacheable
	1 = cacheable and cache-write-proteced
 6	access ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs./RAM(Random Access Memory)	See also DRAM, SRAM. at F0000-FFFFF
	0 = read from ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., write to RAM(Random Access Memory)	See also DRAM, SRAM.
	1 = read from shadow, write is protected
 5	access ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs./RAM(Random Access Memory)	See also DRAM, SRAM. at E0000-EFFFF
	0 = access on-board ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., ATIBM PC AT bus cycle
	1 = access shadow E0000-EFFFF enabled
 4	RAM(Random Access Memory)	See also DRAM, SRAM. at E0000-EFFFF is read-only
 3	access ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs./RAM(Random Access Memory)	See also DRAM, SRAM. at D0000-DFFFF
	0 = access on-board ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., ATIBM PC AT bus cycle
	1 = access shadow D0000-DFFFF enabled
 2	RAM(Random Access Memory)	See also DRAM, SRAM. at D0000-DFFFF is read-only
 1	access ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs./RAM(Random Access Memory)	See also DRAM, SRAM. at C0000-CFFFF
	0 = access on-board ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., ATIBM PC AT bus cycle
	1 = access shadow C0000-CFFFF enabled
 0	RAM(Random Access Memory)	See also DRAM, SRAM. at C0000-CFFFF is read-only
SeeAlso: #P0051
                                                                                

PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX)

0022  RW  index for accesses to data port (see Table P189)
0023  RW  chip set data


(Table P0057)
Values for HP Hornet chipset register index:
 1Eh	buzzer volume/clock oscillator speed
	bit 7-6: buzzer volume
	bit 5-4: system oscillator speed
		00: 10.738636MHz
		01: 15.836773MHz(HP 100/200LX has oscillator with this speed)
		10: 21.477272MHz
		11: 31.673550MHz
 21h	display timing???
 23h	LCD(Liquid Crystal Display) contrast (see INT15h AH=62h)
	valid values: 00h-1fh (1fh is the darkest)
 51h	power adapter status
	bit 7-1: ???
	bit 0: power adapter status(0=inactive/1=active)
 52h	nicad charge status
	bit 7-3: ???
	bit 2: battery charging status(0=???/1=slow charge)
	bit 1-0: ???
 53h	nicad charge status
	bit 7-1: ???
	bit 0: battery charging status(0=???/1=fast charge)
 80h	memory wait for internal ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs.
	valid values: 00h-07h
 81h	memory wait for internal RAM(Random Access Memory)	See also DRAM, SRAM.
	valid values: 00h-03h
 82h	memory wait for external RAM(Random Access Memory)	See also DRAM, SRAM.
	valid values: 00h-0fh
 87h	battery status???
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS
Note:	each access to PORTIBM PC Portable (uses same BIOS as XT) 0023h must immediately follow a write to
	  PORTIBM PC Portable (uses same BIOS as XT) 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0058)
0023  RW  configuration register data


(Table P0058)
Values for Chips&Technologies 82C100/110 configuration register index:
 40h	clock mode/size (see #P0059)
 41h	system configuration (see #P0060)
 42h	configuration valid (see #P0061)
 43h	DIP switch emulation (see #P0062)
 44h-47h substitute NMIsee Non-Maskable Interrupt vector, bytes 0-3
	(these specify the vector to be substituted at the INT 02 vector's
	  memory address whenever an NMIsee Non-Maskable Interrupt occurs, preventing application
	  software from modifying the NMIsee Non-Maskable Interrupt handler)
 48h	refresh timer counter (see #P0063)
 49h	wait state select, refresh enable, keyboard type (see #P0064)
 4Ah	reserved
 4Bh	sleep/memory configuration (see #P0065)
 4Ch	EMSsee Expanded Memory Specification configuration (see #P0066)
 4Dh-4Fh reserved


Bitfields for Chips&Technologies 82C100 clock mode/size register:
Bit(s)	Description	(Table P0059)
 !!!
!!!chips\82c110.pdf p.35
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C100 system configuration register:
Bit(s)	Description	(Table P0060)
 !!!
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C100 configuration valid register:
Bit(s)	Description	(Table P0061)
 !!!
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C110 DIP Switch Emulation register:
Bit(s)	Description	(Table P0062)
 !!!chips\82c110.pdf p.36
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C100 refresh timer count register:
Bit(s)	Description	(Table P0063)
 !!!
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C100 wait state select register:
Bit(s)	Description	(Table P0064)
 !!!
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C100 sleep/memory configuration:
Bit(s)	Description	(Table P0065)
 !!!
SeeAlso: #P0058


Bitfields for Chips&Technologies 82C100 EMSsee Expanded Memory Specification configuration register:
Bit(s)	Description	(Table P0066)
 !!!
SeeAlso: #P0058
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS
Note:	each access to PORTIBM PC Portable (uses same BIOS as XT) 0023h must immediately follow a write to
	  PORTIBM PC Portable (uses same BIOS as XT) 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0067)
0023  RW  configuration register data


(Table P0067)
Values for Chips&Technologies 82C235 configuration register index:
 01h	DMAsee Direct Memory Access wait-state control
 40h	version (read-only)
 41h	clock control
 42h-43h reserved (but listed as read-write in docs)
 44h	peripheral control
 45h	miscellaneous status
 46h	power management
 47h	reserved
 48h	ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. enable
 49h	RAM(Random Access Memory)	See also DRAM, SRAM. write-protect control
 4Ah	shadow RAM(Random Access Memory)	See also DRAM, SRAM. enable 1
 4Bh	shadow RAM(Random Access Memory)	See also DRAM, SRAM. enable 2
 4Ch	shadow RAM(Random Access Memory)	See also DRAM, SRAM. enable 3
 4Dh	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration
 4Eh	extended boundary
 4Fh	EMSsee Expanded Memory Specification control
 !!!chips\82c235.pdf p.87, p.140
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS
Note:	each access to PORTIBM PC Portable (uses same BIOS as XT) 0023h must immediately follow a write to
	  PORTIBM PC Portable (uses same BIOS as XT) 0022h (this is to avoid accidental accesses)

0022  -W  configuration register index (see #P0068)
0023  RW  configuration register data


(Table P0068)
Values for Chips&Technologies 82C311 configuration register index:
 04h	version (read-only)   !!!chips\82c311.pdf p.65
 05h	AT-bus command delay
 06h	AT-bus wait-state control
 08h	identification
 09h	low RAM(Random Access Memory)	See also DRAM, SRAM./ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. configuration
 0Ch	memory enable map (80000h-9FFFFh)
 0Dh	memory enable map (A0000h-BFFFFh)
 0Eh	memory enable map (C0000h-DFFFFh)
 0Fh	memory enable map (E0000h-FFFFFh)
 10h	block 0 type and start address
 11h	block 0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. timing
 12h	block 1 type and start address
 13h	block 1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. timing
 14h	block 2 type and start address
 15h	block 2 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. timing
 16h	block 3 type and start address
 17h	block 3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. timing
 18h	memory block types
 20h	cache control
 21h	directory RAM(Random Access Memory)	See also DRAM, SRAM. control 1
 22h	tag RAM(Random Access Memory)	See also DRAM, SRAM. directory address (low)
 23h	reference location
 24h	SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. configuration/direct access address
 25h	directory RAM(Random Access Memory)	See also DRAM, SRAM. control 2
 26h	READY timeout
 28h	error source/address
 29h	error address (bits 23-16)
 2Ah	memory enable map (00000h-7FFFFh)
 2Bh	miscellaneous control
 2Ch	middle RAM(Random Access Memory)	See also DRAM, SRAM./ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. configuration
 2Fh	page mode posted-write control (82C311 rev. C only)
 30h	block 0 non-cacheable address (bits 23-16)
 31h	block 0 non-cacheable address (bits 15-12) and size
 32h	block 1 non-cacheable address (bits 23-16)
 33h	block 1 non-cacheable address (bits 15-12) and size
 34h	block 2 non-cacheable address (bits 23-16)
 35h	block 2 non-cacheable address (bits 15-12) and size
 36h	block 3 non-cacheable address (bits 23-16)
 37h	block 3 non-cacheable address (bits 15-12) and size
 38h	block 0/1 non-cacheable addresses (bits 26-24)
 39h	block 2/3 non-cacheable addresses (bits 26-24)
 60h	fast reset control
!!!chips\82c311.pdf p.76, p.115
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS
Note:	each access to PORTIBM PC Portable (uses same BIOS as XT) 0023h must immediately follow a write to
	  PORTIBM PC Portable (uses same BIOS as XT) 0022h (this is to avoid accidental accesses)
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C311",PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C316"

0022  -W  configuration register index (see #P0069)
0023  RW  configuration register data


(Table P0069)
Values for Chips&Technologies 82C315 configuration register index:
 07h	processor and bus clock source selection (see #P0070)


Bitfields for C&T 82C315 clock source selection register:
Bit(s)	Description	(Table P0070)
 7-5	reserved (0)
 4	80387 is present
 3	processor clock select
	=0 CLK2IN
	=1 ATIBM PC AT bus state machine clock
 2-0	bus clock source select
	000 CLK2IN/5
	001 CLK2IN/4
	010 CLK2IN/3
	011 CLK2IN/2
	100 ATCLK
SeeAlso: #P0069
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS
Note:	each access to PORTIBM PC Portable (uses same BIOS as XT) 0023h must immediately follow a write to
	  PORTIBM PC Portable (uses same BIOS as XT) 0022h (this is to avoid accidental accesses)
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C311",PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C315",PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C811"

0022  -W  configuration register index (see #P0071)
0023  RW  configuration register data


(Table P0071)
Values for Chips&Technologies 82C316 configuration register index:
 01h	clock/wait-state control	!!!chips\cs8233.pdf p.178
 26h	RTCsee Real-Time Clock/NMIsee Non-Maskable Interrupt/Coprocessor reset	!!!chips\cs8233.pdf p.231
 71h	programmable I/O port 1 address, bits 15-8
 72h	programmable I/O port 1 address, bits 7-0
 73h	programmable I/O port 1 enable
 74h	programmable I/O port 2 address, bits 15-8
 75h	programmable I/O port 2 address, bits 7-0
 76h	programmable I/O port 2 enable
 77h	programmable I/O port 3 address, bits 15-8
 78h	programmable I/O port 3 address, bits 7-0
 79h	programmable I/O port 3 enable
SeeAlso: #P0069
                                                                                

PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS
Note:	many other OPTi chipsets integrate the functionality of the 82C206, and
	  thus support the 82C206's configuration register (e.g. the
	  82C558 from the Viper chipset)

0022  ?W  index for accesses to data port (set to 01h)
0023  RW  chip set data


Bitfields for OPTi 82C206 configuration register 01h:
Bit(s)	Description	(Table P0087)
 7-6	82C206 wait states
	00 1 SYSCLK
	01 2 SYSCLKs
	10 3 SYSCLKs
	11 4 SYSCLKs (default)
 5-4	number of wait states for 16-bit DMAsee Direct Memory Access cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 3-2	number of wait states for 8-bit DMAsee Direct Memory Access cycles
	00 1 wait state (default)
	01 2 wait states
	10 3 wait states
	11 4 wait states
 1	enable early DMAMEMR#
 0	DMAsee Direct Memory Access speed
	0 SYSCLK/2
	1 SYSCLK
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Intel 82091AA Advanced Integrated Peripheral
Range:	PORTIBM PC Portable (uses same BIOS as XT) 0022h (X-Bus), PORTIBM PC Portable (uses same BIOS as XT) 0024h (X-Bus), PORTIBM PC Portable (uses same BIOS as XT) 026Eh (ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA.), or
	  PORTIBM PC Portable (uses same BIOS as XT) 0398h (ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA.)
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0024h"82091AA",PORTIBM PC Portable (uses same BIOS as XT) 026Eh"82091AA",PORTIBM PC Portable (uses same BIOS as XT) 0398h"82091AA"

0022  ?W  configuration register index (see #P0088)
0023  RW  configuration register data


(Table P0088)
Values for Intel 82091AA configuration register index:
 00h	product ID (read-only)
	A0h Intel 82091AA
 01h	product revision (read-only) (see #P0089)
 02h	configuration 1 (see #P0090)
 03h	configuration 2 (see #P0091)
 04h-0Fh reserved
 10h	floppy-disk controller configuration (see #P0092)
 11h	floppy-disk controller power management/status (see #P0093)
 12h-1Fh reserved
 20h	parallel port configuration (see #P0094)
 21h	parallel port power management/status (see #P0095)
 22h-2Fh reserved
 30h	serial port A configuration (see #P0096)
 31h	serial port A power management/status (see #P0097)
 32h-3Fh reserved
 40h	serial port B configuration (see #P0096)
 41h	serial port B power management/status (see #P0097)
 42h-4Fh reserved
 50h	IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. configuration (see #P0098)
 51h-FFh reserved


Bitfields for Intel 82091AA product revision register:
Bit(s)	Description	(Table P0089)
 7-4	stepping number 
 3-0	"dash"-number
SeeAlso: #P0088


Bitfields for Intel 82091AA configuration register 1:
Bit(s)	Description	(Table P0090)
 7	unused (0)
 6	supply voltage (read-only) (1 = 3.3V, 0 = 5.0V)
 5-4	configuration mode
	00 software motherboard
	01 software add-in
	10 extended hardware
	11 basic hardware
 3	configuration address (read-only)
	0 primary address (PORTIBM PC Portable (uses same BIOS as XT) 0022h for X-Bus, PORTIBM PC Portable (uses same BIOS as XT) 026Eh for ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA.)
	1 secondary address (PORTIBM PC Portable (uses same BIOS as XT) 0024h for X-Bus, PORTIBM PC Portable (uses same BIOS as XT) 0398h for ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA.)
 2-1	reserved
 0	power-down AIP's main clock circuitry
SeeAlso: #P0088,#P0091


Bitfields for Intel 82091AA configuration register 2:
Bit(s)	Description	(Table P0091)
 7-3	IRQ7-IRQ3 mode select
	0 = active high (ISA-compatible tri-state drive)
	1 = active low (EISA-compatible open-collector drive)
 2-0	reserved
SeeAlso: #P0088,#P0090


Bitfields for Intel 82091AA floppy-disk controller configuration register:
Bit(s)	Description	(Table P0092)
 7	four floppy drive support enabled (with external decoder)
 6-2	reserved
 1	FDC address
	0 = primary (03F0h)
	1 = secondary (0370h)
 0	enable FDC
SeeAlso: #P0088,#P0093


Bitfields for Intel 82091AA floppy-disk controller power management register:
Bit(s)	Description	(Table P0093)
 7-4	reserved
 3	enable FDC auto-powerdown on idle
 2	reset FDC
	(this bit must be pulsed, remaining high for at least 1.2 us)
 1	(read-only) FDC is idle
 0	power-down FDC
Note:	to restore FDC from explicit powerdown via bit 0, clear bit 0, then
	  reset the FDC using bit 2 (hardware reset) or using a software reset
	  (FDC's DOR bit 2 or DSR bit 7)
SeeAlso: #P0088,#P0092


Bitfields for Intel 82091AA parallel port configuration:
Bit(s)	Description	(Table P0094)
 7	FIFO threshold
	0 = 8 slots in each direction
	1 = one slot forward, 15 reverse
 6-5	parallel-port hardware mode
	00 ISA-compatible
	01 PSIBM PS/2, any model/2-compatible
	10 EPP
	11 ECP (read only -- ECP mode must be set via ECP Extended Control Reg)
 4	reserved
 3	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. select
	0 = IRQ5
	1 = IRQ7
 2-1	address select
	00 PORTIBM PC Portable (uses same BIOS as XT) 0378h-037Bh
	01 PORTIBM PC Portable (uses same BIOS as XT) 0278h-027Bh
	10 PORTIBM PC Portable (uses same BIOS as XT) 03BCh-03BEh (not for EPP mode)
	11 reserved
 0	enable parallel port
SeeAlso: #P0088,#P0095,#P0920,PORTIBM PC Portable (uses same BIOS as XT) 0678h"ECP"


Bitfields for Intel 82091AA parallel port power managment register:
Bit(s)	Description	(Table P0095)
 7-6	reserved
 5	FIFO overrun or underrun has occurred
	this bit is cleared by resetting the port via bit 2
 4	reserved
 3	enable auto-powerdown
 2	reset parallel port (pulse this bit; must remain high for 1.13 us)
 1	(read-only) parallel port is idle
 0	power-down parallel port
Note:	an explicit power-down may be canceled by either clearing bit 0 or
	  pulsing bit 2 to reset the port
SeeAlso: #P0088,#P0094


Bitfields for Intel 82091AA serial port configuration:
Bit(s)	Description	(Table P0096)
 7	enable 2MHz MIDI(Musical Instrument Digital Interface) A standardized interface for controlling musical instruments with a computer. clock for MIDI(Musical Instrument Digital Interface) A standardized interface for controlling musical instruments with a computer. baud rate
 6-5	reserved
 4	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. select
	0 = IRQ3
	1 = IRQ4
 3-1	address select
	000 PORTIBM PC Portable (uses same BIOS as XT) 03F8h-03FFh
	001 PORTIBM PC Portable (uses same BIOS as XT) 02F8h-02FFh
	010 PORTIBM PC Portable (uses same BIOS as XT) 0220h-0227h
	011 PORTIBM PC Portable (uses same BIOS as XT) 0228h-022Fh
	100 PORTIBM PC Portable (uses same BIOS as XT) 0238h-023Fh
	101 PORTIBM PC Portable (uses same BIOS as XT) 02E8h-02EFh
	110 PORTIBM PC Portable (uses same BIOS as XT) 0338h-033Fh
	111 PORTIBM PC Portable (uses same BIOS as XT) 03E8h-03EFh
 0	enable serial port
Note:	although it is possible to configure both serial ports at the same
	  address, this is not recommended because the 82091AA disables serial
	  port B without placing it into powerdown mode
SeeAlso: #P0088,#P0097


Bitfields for Intel 82091AA serial port power management register:
Bit(s)	Description	(Table P0097)
 7-5	reserved
 4	enable test mode
	when enabled, and DLAB bit in LCR is set, the baud rate clock is output
	  on the SOUTA pin
 3	enable auto-powerdown on idle
 2	reset serial port (should be pulsed, high for at least 1.13 us)
 1	(read-only) serial port is idle
 0	power-down serial port
Notes:	setting powerdown mode via bit 0 resets both receiver and transmitter,
	  including the FIFOs, so software should check that port is idle
	  before powering it down
	the serial port may be brought out of an explicit powerdown by either
	  clearing bit 0 or pulsing bit 2
SeeAlso: #P0088,#P0096


Bitfields for Intel 82091AA IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. configuration:
Bit(s)	Description	(Table P0098)
 7-3	reserved
 2	enable both primary and secondary addresses
 1	address select (when bit 2 is clear)
	0 PORTIBM PC Portable (uses same BIOS as XT) 01F0h-01F7h and 03F6h (primary)
	1 PORTIBM PC Portable (uses same BIOS as XT) 0170h-0177h and 0376h (secondary)
 0	enable IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. interface
 !!!intel\29048603.pdf p.45
SeeAlso: #P0088,#P0092