PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips

0022  ?W  index for accesses to data port
0024  RW  chip set data
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi 82C281/282/283 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0099)
0024  RW  chip set data


(Table P0099)
Values for OPTi 82C281/82C282/82C283 configuration register index:
 10h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register (see #P0100)
 11h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register (see #P0101)
 12h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 2 (see #P0102)
 13h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 3 (see #P0103)
 14h	miscellaneous control register (see #P0104)
 15h	cache control register (see #P0105)
 16h	cache control register 2 (see #P0106)


Bitfields for OPTi 82C281/282/283 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register:
Bit(s)	Description	(Table P0100)
 7-6	82C281/2 revision number (read-only)
 7	82C283 revision (0 = A, 1 = B)
 6	82C283A: reserved
	82C283B: DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. is pipelined
 5	local DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read wait states
	82C281/2: 0=one, 1=two	  82C283: 0=none, 1=one
 4	local DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. write wait states
	82C281/2: 0=one, 1=two	  82C283: 0=none, 1=one
 3-0	local DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. memory configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	0001	256K	256K	256K	256K
	0010	256K	256K	1M	-
	0011	256K	256K	1M	1M
	0100	256K	256K	4M	-
	0101	1M	-	-	-
	0110	1M	1M	-	-
	0111	1M	1M	1M	-
	1000	1M	1M	1M	1M
	1001	1M	4M	-	-
	1010	1M	1M	4M	-
	1011	4M	4M	-	-
	1100	4M	-	-	-  (82C283B only)
	1111	256K	256K	-	-
SeeAlso: #P0099


Bitfields for OPTi 82C281 shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register:
Bit(s)	Description	(Table P0101)
 7	BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. F000-FFFF shadowing
	0 read-only from shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 read from ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., write to shadow RAM(Random Access Memory)	See also DRAM, SRAM.
 6	adapter ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at E000-EFFF
	0 disable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 shadow RAM(Random Access Memory)	See also DRAM, SRAM. selectively enabled by configuration register 12h
	  (see #P0102)
 5	adapter ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at D000-DFFF
	0 disable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 shadow RAM(Random Access Memory)	See also DRAM, SRAM. selectively enabled by configuration register 12h
 4	adapter ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at C000-CFFF
	0 disable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 shadow RAM(Random Access Memory)	See also DRAM, SRAM. selectively enabled by configuration register 13h
	  (see #P0103)
 3	shadow RAM(Random Access Memory)	See also DRAM, SRAM. Copy Enable control (C000-EFFF)
	0 write to expansion bus
	1 write to local DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
 2	shadow RAM(Random Access Memory)	See also DRAM, SRAM. E000-EFFF writeability
	0 read/write
	1 read-only
 1	shadow RAM(Random Access Memory)	See also DRAM, SRAM. D000-DFFF writeability
	0 read/write
	1 read-only
 0	shadow RAM(Random Access Memory)	See also DRAM, SRAM. C000-CFFF writeability
	0 read/write
	1 read-only
SeeAlso: #P0099,#P0102


Bitfields for OPTi 82C281 shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 2:
Bit(s)	Description	(Table P0102)
 7	enable EC00-EFFF
 6	enable E800-EBFF
 5	enable E400-E7FF
 4	enable E000-E3FF
 3	enable DC00-DFFF
 2	enable D800-DBFF
 1	enable D400-D7FF
 0	enable D000-D3FF
Note:	bits 7-4 are only in effect when register 11h bit 6 is set; bits 3-0
	  are only in effect when register 11h bit 5 is set
SeeAlso: #P0099,#P0101,#P0103


Bitfields for OPTi 82C281 shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 3:
Bit(s)	Description	(Table P0103)
 7	enable CC00-CFFF
 6	enable C800-CBFF
 5	enable C400-C7FF
 4	enable C000-C3FF
 3-0	unused shadow RAM(Random Access Memory)	See also DRAM, SRAM. remap address; supplies bits 23-20 of
	  address at which to map A000-BFFFF and D000-EFFF is not used
	  for shadowing (except if this field is set to 0, the remapping
	  is disabled)
SeeAlso: #P0099,#P0101,#P0102


Bitfields for OPTi 82C281 miscellaneous control register:
Bit(s)	Description	(Table P0104)
 7	allow F0000-F0FFF to be written even while F0000-FFFFF is
	  write-protected ("Zenith mode")
 6	keyboard reset control
	=1 HLT must be executed before 82C281 generates CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reset from
	    keyboard controller Reset command
 5	master byte swap enable
 4	82C281/2: fast NMIsee Non-Maskable Interrupt request
	82C283A: reserved (0)
	82C283B: ATCLK setting (=0 from register 14h bit 0; =1 CLK/8)
 3	82C281/2/3A: reserved
	82C283B: on-board DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. parity error enable
 2	enable slow refresh mode
	(every 95.5 us (281/282) or 63.6 us (283) instead of 15.9 us)
 1	enable turbo switch function
 0	clock select
	=0 ATCLK2 = CPUCLK2 / 6
	=1 ATCLK2 = CPUCLK2 / 4
SeeAlso: #P0099


Bitfields for OPTi 82C281/82C282 cache control register:
Bit(s)	Description	(Table P0105)
 7	enable cache
 6	reserved (0)
 5	enable posted write (82C281 only)
 4	ALL accesses are non-cacheable
 3	reserved (0)
 2-0	non-cacheable region size (see also #P0106)
	000  64K
	001 128K
	...
	101  4M
	110  8M
	111 disabled
SeeAlso: #P0099,#P0106


Bitfields for OPTi 82C281/82C282 cache control register 2:
Bit(s)	Description	(Table P0106)
 7-0	starting address bits 23-16 of non-cacheable region
Note:	the specified starting address must be a multiple of the region size
SeeAlso: #P0099,#P0105
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi 82C291/82C295 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0107)
0024  RW  chip set data


(Table P0107)
Values for OPTi 82C291/82C295 configuration register index:
 20h	Revision/ATIBM PC AT Bus configuration register (see #P0108)
 21h	System Control register (see #P0109)
 22h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register (see #P0110)
 23h	ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. Chip Select Control register (see #P0111)
 24h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register E (see #P0112)
 25h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register D (see #P0113)
 26h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register C (see #P0114)
 27h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Write Protect/Remap Area (see #P0115)
 28h	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register (see #P0116)
 29h	Cacheable Upper Bound register (see #P0117)
 2Ah	Non-Cacheable Segments register 1 (see #P0118)
 2Bh	Non-Cacheable Segments register 2 (see #P0119)
 2Ch	Non-Cacheable Segments register 3 (see #P0120)


Bitfields for OPTi 82C291/82C295 ATIBM PC AT Bus configuration register:
Bit(s)	Description	(Table P0108)
 7-6	82C291/295 revision (read-only)
 5-4	back-to-back I/O recovery time
	00-11 = 3-6 ATCLKs between I/O accesses
 3	enable slow refresh mode
 2	enable hidden refresh
 1-0	ATIBM PC AT clock selection
	00 ATCLK = CLK2 / 10
	01 ATCLK = CLK2 / 8
	10 ATCLK = CLK2 / 6
	11 ATCLK = CLK2 / 4
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 System Control register:
Bit(s)	Description	(Table P0109)
 7	ATIBM PC AT bus master byte swap enabled
 6	ALE generation for each ATIBM PC AT cycle
	0 a new ALE will be generated during bus conversion cycles
	1 multiple ALEs will be generated during bus conversion cycles
 5	keyboard fast reset emulation control
	0 enable, a "Halt" is required before a fast CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reset is generated
	1 disable, fast CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reset is generated directly after the "FE" I/O
	  command to port 64h is decoded
 4	ATIBM PC AT cycle additional wait state
	0 disable, standard ATIBM PC AT cycle
	1 enable, inserts one extra wait state in standard ATIBM PC AT bus cycle
 3-2	reserved
 1	local device ready control
	0 RDYI# input to the 82C291 will be synchronized and set as RDY# to
	  the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. one T-state delayed
	1 RDYI# input to the 82C291 will not be output to the CPU(Central Processing Unit) The microprocessor which executes programs on your computer.. RDY# from
	  the local device must be directed to the 82C291 and the CPU(Central Processing Unit) The microprocessor which executes programs on your computer.
 0	system memory parity checking
	0 disable, no parity checking	     
	1 enable, will check parity
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Configuration register:
Bit(s)	Description	(Table P0110)
 7-6	number of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read cycle wait states
 5-4	number of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. write cycle wait states
 3-0	Banks 0 thru 3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	0000	256K	256KB	-	-
	0001	256K	256K	256K	256K
	0010	256K	256K	1M	-
	0011	256K	256K	1M	1M
	0100	256K	256K	4M	-
	0101	1M	-	-	-
	0110	1M	1M	-	-
	0111	1M	1M	1M	-
	1000	1M	1M	1M	1M
	1001	1M	4M	-	-
	1010	1M	1M	4M	-
	1011	4M	-	-	-
	1100	4M	4M	-	-
	1101	reserved
	1110	reserved
	1111	reserved
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. Chip Select Control register:
Bit(s)	Description	(Table P0111)
 7	enable ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. Chip Select for write cycles (to support flash ROMs)
 6	enable ROMCS# for 0F0000-0FFFFF segments
 5	enable ROMCS# for 0E8000-0EFFFF segments
 4	enable ROMCS# for 0E0000-0E7FFF segments
 3	enable ROMCS# for 0D8000-0DFFFF segments
 2	enable ROMCS# for 0D0000-0D7FFF segments
 1	enable ROMCS# for 0C8000-0CFFFF segments
 0	enable ROMCS# for 0C0000-0C7FFF segments
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register E:
Bit(s)	Description	(Table P0112)
 7	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for EC000-EFFFF segments
 6	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for E8000-EBFFF segments
 5	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for E4000-E7FFF segments
 4	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for E0000-E3FFF segments
 3	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for EC000-EFFFF segments
 2	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for E8000-EBFFF segments
 1	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for E4000-E7FFF segments
 0	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for E0000-E3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as E4000-E7000.
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register D:
Bit(s)	Description	(Table P0113)
 7	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for DC000-DFFFF segments
 6	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for D8000-DBFFF segments
 5	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for D4000-D7FFF segments
 4	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for D0000-D3FFF segments
 3	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for DC000-DFFFF segments
 2	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for D8000-DBFFF segments
 1	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for D4000-D7FFF segments
 0	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for D0000-D3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as D4000-D7000.
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register C:
Bit(s)	Description	(Table P0114)
 7	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for CC000-CFFFF segments
 6	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for C8000-CBFFF segments
 5	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for C4000-C7FFF segments
 4	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. reads for C0000-C3FFF segments
 3	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for CC000-CFFFF segments
 2	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for C8000-CBFFF segments
 1	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for C4000-C7FFF segments
 0	enable shadow RAM(Random Access Memory)	See also DRAM, SRAM. writes for C0000-C3FFF segments
Note:	OPTi documentation incorrectly states the segment range for bits 5
	  and 1 as C4000-C7000.
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Write Protect/Remap Area:
Bit(s)	Description	(Table P0115)
 7	enable Write Protect for F0000-FFFFF segments
 6	enable Write Protect for E0000-EFFFF segments
 5	enable Write Protect for D0000-DFFFF segments
 4	enable Write Protect for C0000-CFFFF segments
 3-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. remap starting address, bits 23-20
	0000  disabled, no mapping
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register:
Bit(s)	Description	(Table P0116)
 7	enable write-back cache controller operation
 6	enable DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. performance mode
	this bit should not be enabled unless external cache is disabled
	  (intended to optimize DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. performance)
 5	enable all memory accesses no-cacheable mode
 4	enable 640K-1M area no-cacheable mode
 3-2	cache timing control bits
	00 invalid
	01 0 wait state cache write w/o CAWE# extended, use when 8K*8 SRAMs
	10 1 wait state cache write hit
	11 0 wait state cache write hit with CAWE# extended when 32K*8 SRAMs
 1-0	cache size/cacheable DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	00  16K /  2M
	01  32K /  4M
	10  64K /  8M
	11 128K / 16M
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 Cacheable Upper Bound register:
Bit(s)	Description	(Table P0117)
 7-4	reserved
 3-0	cacheable upper bound address, bits 23-20
	0000  feature disabled
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0107


Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 1:
Bit(s)	Description	(Table P0118)
 7	enable non-cacheable segment A
 6-4	size of no-cacheable memory segment A
	000  64K
	001 128K
	010 256K
	011 512K
	100   1M
	101   2M
	110   4M
	111   8M
 3	enable non-cacheable segment B
 2-0	size of no-cacheable memory segment B (same values as bits 6-4)
SeeAlso: #P0107,#P0119
    

Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 2:
Bit(s)	Description	(Table P0119)
 7-0	address bits 23-16 for starting address of non-cacheable memory
	  segment A
SeeAlso: #P0107,#P0118,#P0120


Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 3:
Bit(s)	Description	(Table P0120)
 7-0	address bits 23-16 for starting address of non-cacheable memory
	  segment B
SeeAlso: #P0107,#P0118,#P0119
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi 82C381/82C382 CHIPSETS - CONFIGURATION REGISTERS
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0121)
0024  RW  chip set data


(Table P0121)
Values for OPTi 82C381/82C382 configuration register index:
 00h	clock selects (see #P0122)
 01h	reset control (see #P0123)
 10h	remapping address (see #P0124)
 11h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0125)
 12h	memory enable (see #P0126)
 13h	bank configuration (see #P0127)
 14h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration (see #P0128)
 15h	video adapter shadow (see #P0129)
 16h	fast GateA20 (see #P0130)
 17h	cache configuration (see #P0131)
 18h	non-cacheable block 1 size (see #P0132)
 19h	non-cacheable block 1 address (see #P0133)
 1Ah	non-cacheable block 2 size (see #P0132)
 1Bh	non-cacheable block 2 address (see #P0133)
 1Ch	cacheable area (see #P0134)
Note:	registers 00h and 01h address the 82C381, the remaining registers
	  address the 82C382
SeeAlso: #P0189


Bitfields for OPTi 82C381/82C382 clock selects:
Bit(s)	Description	(Table P0122)
 7-6	cache controller enable
	00 cache controller disabled (default)
	01 cache controller disabled; PPCS#, SPCS#, NPCS# signals are
	      active if selected
	10 external cache controller installed
	11 on-chip cache controller installed
 5	hot CPU(Central Processing Unit) The microprocessor which executes programs on your computer. reset (low->high transition generates reset)
 4	enable ATCLK stretch
 3	turbo clock
	=0 CLKIN is CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock
	=1 HIGH pin selected clock (HIGH=0: CLKIN, HIGH=1: ICLK)
 2-1	ICLK clock select
	00 CLKIN/4 (default)
	01 CLKIN/3
	10 CLKIN/2
	11 reserved
 0	master byte swap enable (default = 0)
SeeAlso: #P0121,#P0123


Bitfields for OPTi 82C381/82C382 reset control:
Bit(s)	Description	(Table P0123)
 7-2	reserved
 1	RESET3 control
	=1 generate RESET3 on RESET2 only after a HLT instruction
	=0 generate RESET3 immediately on RESET2 (default)
 0	activate cache controller FLUSH# pin (default = 1)
SeeAlso: #P0121,#P0122,#P0124


Bitfields for OPTi 82C381/82C382 remapping address:
Bit(s)	Description	(Table P0124)
 7-5	reserved
 4	enable remapping
 3-0	remap address range, bits 23-20
	0000  no mapping
	0001  1M
	0010  2M
	...
	1111 15M
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 shadow RAM(Random Access Memory)	See also DRAM, SRAM. control:
Bit(s)	Description	(Table P0125)
 7	BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at F0000-FFFFF Shadowing
	0 read only from shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 read from ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., write to shadow RAM(Random Access Memory)	See also DRAM, SRAM.
 6	ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at D0000-DFFFF
	0 disable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 shadow RAM(Random Access Memory)	See also DRAM, SRAM. selectively enabled by configuration register 12h
 5	Adaptor ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at E0000-EFFFF
	0 disable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 shadow RAM(Random Access Memory)	See also DRAM, SRAM. selectively enabled by configuration register 12h
 4	write-protect shadow RAM(Random Access Memory)	See also DRAM, SRAM. at D0000h-DFFFFh (default = not protected)
 3	write-protect shadow RAM(Random Access Memory)	See also DRAM, SRAM. at E0000h-EFFFFh
 2	enable Timeout precharge counter 
 1-0	reserved
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 memory enable:
Bit(s)	Description	(Table P0126)
 7	enable EC000-EFFFF
 6	enable E8000-EBFFF
 5	enable E4000-E7FFF
 4	enable E0000-E3FFF
 3	enable DC000-DFFFF
 2	enable D8000-DBFFF
 1	enable D4000-D7FFF
 0	enable D0000-D3FFF
Note:	0 = disable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. (default), 1 = enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM.
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 memory bank configuration:
Bit(s)	Description	(Table P0127)
 7	Reserved
 6-4	Bank0 and Bank1 configuration
	(val)	Bank0	 Bank1 
	000	256K	 -  
	001	256K	 256K
	010	256K	 1M  
	011	1M	 256K
	100	1M	 -  
	101	1M	 1M 
	110	-	 -  
	111	256K	 - 
 3	reserved
 2-0	Bank2 and Bank3 configuration
	(val)	Bank2	 Bank3 
	000	256K	 -  
	001	256K	 256K
	010	-	 -  
	011	1M	 256K
	100	1M	 -  
	101	1M	 1M 
	11X	-	 -  
SeeAlso: #P0121,#P0128


Bitfields for OPTi 82C381/82C382 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration:
Bit(s)	Description	(Table P0128)
 7,6	number of read cycle wait states (default = 01)
 5	write cycle wait state
	0 = 0 wait 
	1 = 1 wait (default)	  
 4-0	reserved	
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 video adapter shadow:
Bit(s)	Description	(Table P0129)
 7	reserved
 6	copy enable for C0000-EFFFF
	0 write to ATIBM PC AT Channel (default) 
	1 write to local DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
 5	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C0000-CFFFF writability
	0 read/write (default)
	1 read only
 4	ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. at C0000-CFFFF
	0 disable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
	1 shadow RAM(Random Access Memory)	See also DRAM, SRAM. selectively enabled by Bits<0:3> (default)
 3	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at CC000-CFFFF
 2	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C8000-CbFFF
 1	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C4000-C7FFF
 0	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C0000-C3FFF
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 fast GateA20 control:
Bit(s)	Description	(Table P0130)
 7-4	Reserved
 3	Fast GateA20 Control  
	0 Signal controled by GATEA20 signal from Keyboard Controler
	1 CPUA20 enabled onto GA20
 2-0	reserved	
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 cache configuration:
Bit(s)	Description	(Table P0131)
 7	force NCA* Output Pin low
	if this bit is clear, it has no effect on NCA* Output Pin
 6	enable CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through.
 5	write-through cache (Note: this bit must be set)
 4-3	line size
	00  4 bytes 
	01  8 bytes
	10  16 bytes
	11  reserved
 2-0	reserved	
SeeAlso: #P0121


Bitfields for OPTi 82C381/82C382 non-cacheable block size:
Bit(s)	Description	(Table P0132)
 7-5	block size
	000 64K
	001 128K
	010 256K
	011 512K
	100 1M
	101 4M (block 1 only)
	101 reserved (block 2 only)
	110 8M (block 1 only)
	110 reserved (block 2 only)
	111 disabled (default)
 4-0	reserved (0)
SeeAlso: #P0121,#P0131,#P0133


Bitfields for OPTi 82C381/82C382 non-cacheable block address:
Bit(s)	Description	(Table P0133)
 7-0	bits 23-16 of non-cacheable block's address
Note:	the selected address must be a multiple of the block size
	  selected by register 18h/1Ah
SeeAlso: #P0121,#P0132,#P0134


Bitfields for OPTi 82C381/82C382 cacheable area:
Bit(s)	Description	(Table P0134)
 7-4	cacheable address range
	0000 16M
	0001 1M
	0010 2M
	0011 3M
	...
	1111 15M
 3	256K remapped area is cacheable
 2-0	reserved
SeeAlso: #P0121
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi 82C463MV CHIPSET - CONFIGURATION REGISTERS
Desc:	the 82C463MV contains a memory control unit (MCU), an ATIBM PC AT Bus
	  Control Unit (BCU), a Power Management Unit (PMU), data
	  buffers and a 82C206 type IPC(Inter-Process Communication) Any one of numerous methods for allowing two or more separate processes to exchange data. (without real time clock)
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0135)
0024  RW  chip set data


(Table P0135)
Values for OPTi 82C463MV configuration register index:
 30h	general control 1 (see #P0136)
 31h	general control 2 (see #P0137)
 32h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. control 1 (see #P0138)
 33h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. control 2 (see #P0139)
 34h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. size (see #P0140)
 35h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. timing and caching control (see #P0141)
 36h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. control 3 (see #P0142)
 37h	D000h and E000h segment access control (see #P0143)
 38h	non-cacheable block 1 size, controls and address bit A24 (see #P0144)
 39h	non-cacheable block 1 address bits A23-A16
 3Ah	non-cacheable block 2 size and address bit A24 (see #P0145)
 3Bh	non-cacheable block 2 address bits A23-A16
 3Ch-3Fh	reserved
 40h	PMU control 1 (see #P0146)
 41h	PMU control 2: doze timer (see #P0147)
 42h	PMU control 3: other timers (see #P0148)
 43h	PMU control 4 (see #P0149)
 44h	LCD(Liquid Crystal Display) timer count (should not be loaded with a value <5)
 45h	disk timer count (should not be loaded with a value <5)
 46h	keyboard timer count (should not be loaded with a value <5)
 47h	GNR_ACCESS timer count (should not be loaded with a value <5)
 48h	GNR_ACCESS I/O base address (lines A8-A1, A0 is a "don't care")
 49h	GNR_ACCESS control and I/O base address line A9 (see #P0150)
 4Ah	CSG0# base address (lines A8-A1, A0 is a "don't care")
 4Bh	CSG0# control and base address line A9 (see #P0151)
 4Ch	CSG1# base address (lines A8-A1, A0 is a "don't care")
 4Dh	CSG1# control and base address line A9 (see #P0152)
 4Eh	idle timer control (see #P0153)
 4Fh	idle timer count (should not be loaded with a value <5)
 50h	suspend/resume control (see #P0154)
 51h	beeper/sequencer control (see #P0155)
 52h	PMU general-purpose storage 1
 53h	PMU general-purpose storage 2
 54h	PMU Periferal Power (PPWR) control 1 (see #P0156)
 55h	PMU Periferal Power (PPWR) control 2 (see #P0157)
 56h	PIO control 1 (see #P0158)
 57h	PIO control 2 (see #P0159)
 58h	PMU event control 1 (see #P0160)
 59h	PMU event control 2 (see #P0161)
 5Ah	PMU event control 3 (see #P0162)
 5Bh	PMU event control 4 (see #P0163)
 5Ch	SMI source (low) (see #P0164)
 5Dh	SMI source (high) (see #P0165)
 5Eh	clock stretching control (see #P0166)
 5Fh	resume interrupt control (see #P0167)
 60h	software sequencer address (write only)
 61h	debounce control (see #P0168)
 62h	doze-mode IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (see #P0169)
 63h	idle timer IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (see #P0170)
 64h	PMI#6 IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. select (see #P0171)
 65h	doze-mode configuration (see #P0172)
 66h	suspend control (see #P0173)
 67h	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. frequency (see #P0174)
 68h	timer clock source (see #P0175)
 69h	R_TIMER count (should not be loaded with a value <5)
 6Ah	resume IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (see #P0176)
 6Bh	resume sources (see #P0177)
 6Ch-6Fh	TMP0 - TMP3


Bitfields for 82C463MV general control 1 (register 30h):
Bit(s)	Description	(Table P0136)
 7-6	chipset revision number (read only)
 5	MASTER#/RI pin function (RI = modem Ring Indicator)
	=1 RI (default)
	=0 MASTER#
 4	enable turbo VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.
 3	enable global relocation/translation for SMI addresses (see also
	  register 31h bit 4 at #P0137)
 2	enable extra wait state in ATIBM PC AT cycle
 1	fast reset control
	  =1 does not require Halt instruction
	  =0 requires Halt instruction before generation of CPURST (SRESET
	       if Intel SL Enhanced or Cyrix Cx486S/S2 CPUs
 0	reserved (0)
SeeAlso: #P0135


Bitfields for 82C463MV general control 2 (register 31h):
Bit(s)	Description	(Table P0137)
 7	enable master byte swap
 6	reserved, read-only (1)
 5	disable parity check
 4	Dynamic SMI relocation
	  if no SMI sequence is running
	    =1 allow relocation of addresses from the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. in the 3000h/4000h
	       segment to the B000h/A000h SMI memory space
	    =0 disable relocation
	  if SMI sequence is running (qualified by SMIACT#)
	    =1 allow data accesses to the 3000h and 4000h segments
	    =0 relocate all accesses in the 3000h/4000h segment to the
	       B000h/A000h SMI segment (normal operation)
	  if SMI sequence is running (qualified by SMIADS#)
	    =1 not allowed
	    =0 for a SMIADS# cycle, relocate all accesses in the 6000h/7000h
	       segment to the A000h/B000h SMI segment
	       for a normal ADS# operation, there is no relocation
 3	EC000h-EFFFFh access control
	if register 36h bit 6=0
	  =1 R/W from ROMCS#
	  =0 R/W from AT-Bus
	if register 36h bit 6=1
	  =1 Read from ROMCS# if not shadowed (see register 33h bits 7-4),
		write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	  =0 Read from AT-Bus if not shadowed (see register 33h bits 7-4),
		write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
 2	E8000h-EBFFFh access control (see bit 3)
 1	E4000h-E7FFFh access control (see bit 3)
 0	E0000h-E3FFFh access control (see bit 3)
SeeAlso: #P0135,#P0139,#P0142


Bitfields for 82C463MV shadow RAM(Random Access Memory)	See also DRAM, SRAM. control 1 (register 32h):
Bit(s)	Description	(Table P0138)
 7	segment F000h access control
	  =1 read from ROMCS#, write to ROMCS# (if register 36h bit 7=1)
	     or DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. (if register 36h bit 7=0)
	  =0 read from DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. and write protect (enable shadowing)
 6-5	reserved (1)
 4	write protect segment D000h
 3	write protect segment E000h
 2	reserved, read-only (1)
 1	reserved (0)
 0	ALE control
	  =1 single ALE during bus conversion
	  =0 multiple ALE
SeeAlso: #P0135,#P0142,#P0139


Bitfields for 82C463MV shadow RAM(Random Access Memory)	See also DRAM, SRAM. control 2 (register 33h):
Bit(s)	Description	(Table P0139)
 7	enable shadowing for EC000h-EFFFFh
 6	enable shadowing for E8000h-EBFFFh
 5	enable shadowing for E4000h-E7FFFh
 4	enable shadowing for E0000h-E3FFFh
 3	enable shadowing for DC000h-DFFFFh
 2	enable shadowing for D8000h-DBFFFh
 1	enable shadowing for D4000h-D7FFFh
 0	enable shadowing for D0000h-D3FFFh
SeeAlso: #P0135,#P0138


Bitfields for 82C463MV DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. size (register 34h):
Bit(s)	Description	(Table P0140)
 7-4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Bank 0 and 1 Size
	0000 256K, unused
	0001 256K, 256K
	0010 256K, 1M
	0011 256K, 4M
	0100 512K, unused
	0101 512K, 512K
	0110 512K, 1M
	0111 512K, 4M
	1000 1M, unused
	1001 1M, 1M
	1010 1M, 4M
	1011 4M, 1M
	1100 4M, unused
	1101 4M, 4M
	1110 1M, 2M
	1111 both unused
 3-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Bank 2 and 3 Size
	0000 1M, unused
	0001 1M, 1M
	0010 1M, 4M
	0011 4M, 4M
	0100 4M, unused
	0101 both unused
	0110 1M, 2M
	0111 512K, 512K
	10xx both unused
	110x both unused
	1110 2M, unused
	1111 2M, 2M (default)
SeeAlso: #P0135


Bitfields for 82C463MV DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. timing and caching control (register 35h):
Bit(s)	Description	(Table P0141)
 7-6	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read wait states
	00 = 0 wait states, burst mode 2-1-1-1
	01 = 1 wait state, burst mode 3-1-1-1
	10 = 1 wait state, burst mode 3-2-2-2
	11 = 2 wait states, burst mode 4-3-3-3 (default)
 5-4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. write wait states
	00 = 0 wait states
	01 = 1 wait state
	10 = 2 wait states
	11 = reserved (default)
 3	MP2/STRAP2 status (read-only)
	=1 1X Clock
	=0 2X Clock
 2	disable caching of F000h segment (this bit is effective only when
	  register 32h bit 7 =0)
 1	global DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. cache control (1=disable, default)
 0	disable caching of C0000h-C7FFFh (default)
SeeAlso: #P0135,#P0138


Bitfields for 82C463MV shadow RAM(Random Access Memory)	See also DRAM, SRAM. control 3 (register 36h):
Bit	Description	(Table P0142)
 7	segment F000h write control
	=1 write to ROMCS#
	=0 write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	don't care if register 32h bit 7=0
 6	C0000h-EFFFFh control
	=1 read from AT-Bus or ROMCS# (if ROMCS# is enabled to that block),
	  write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	=0 R/W from ATIBM PC AT bus or ROMCS# (if ROMCS# is enabled to that block)
 5	write protect segment C000h
 4	reserved (1)
 3	enable shadowing for CC000h-CFFFFh
 2	enable shadowing for C8000h-CBFFFh
 1	enable shadowing for C4000h-C7FFFh
 0	enable shadowing for C0000h-C3FFFh
SeeAlso: #P0135,#P0138


Bitfields for 82C463MV D000h and E000h segments access control (register 37h):
Bit	Description	(Table P0143)
 7	DC000h-DFFFFh access control
	if register 36h bit 6=1
	    =1 read from ROMCS# if not shadowed, write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	    =0 read from AT-Bus if not shadowed, write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	if register 36h bit 6=0
	    =1 R/W from ROMCS#
	    =0 R/W from AT-Bus
 6	D8000h-DBFFFh access control (see bit 7)
 5	D4000h-D7FFFh access control (see bit 7)
 4	D0000h-D3FFFh access control (see bit 7)
 3	disable caching for EC000h-EFFFFh (default)
 2	disable caching for E8000h-EBFFFh (default)
 1	disable caching for E4000h-E7FFFh (default)
 0	disable caching for E0000h-E3FFFh (default)
SeeAlso: #P0135,#P0142


Bitfields for non-cacheable block 1 size, control and A24 (register 38h):
Bit(s)	Description	(Table P0144)
 7-5	size of non-cacheable memory block 1
	000 64K
	001 128K
	010 256K
	011 1M
	1xx disabled (default)
 4	CC000h-CFFFFh access control
	if register 36h bit 6=1
	    =1 read from ROMCS# if not shadowed, write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	    =0 read from AT-Bus if not shadowed, write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	if register 36h bit 6=0
	    =1 R/W from ROMCS#
	    =0 R/W from AT-Bus
 3	C8000h-CBFFFh access control (see bit 4)
 2	C4000h-C7FFFh access control (see bit 4)
 1	C0000h-C3FFFh access control (see bit 4)
 0	address bit A24 of non-cacheable memory block 1
SeeAlso: #P0135,#P0142


Bitfields for non-cacheable block 2 size and A24 (register 3Ah):
Bit(s)	Description	(Table P0145)
 7-5	size of non-cacheable memory block 2
	000 64K
	001 128K
	010 256K
	011 1M
	1xx disabled (default)
 4	unused
 3	enable internal HLDA latch during stop clock (must be disabled
	  before DMAsee Direct Memory Access transfers are performed)
 2	reserved (1)
 1	unused
 0	address bit A24 of non-cacheable memory block 2
SeeAlso: #P0135


Bitfields for 82C463MV PMU control 1 (register 40h):
Bit	Description	(Table P0146)
 7	Reset/SMI indication (read-only)
	=1 the last read or fetch from address XXXFFFF0h was a SMIADS#
	     cycle
	=0 the last read or fetch from address XXXFFFF0h was a regular
	     ADS# cycle
 6	divide global timer by 4
 5	LLOWBAT polarity selector
	=1 low active
	=0 high active
 4	LOWBAT polarity selector (see bit 5)
 3	SQWIN input clock frequency
	=1 128KHz
	=0 32KHz
 2	external EPMI2 pin polarity
	=1 active low
	=0 active high
 1	external EPMI1 pin polarity (see bit 2)
 0	send reset pulse during resume
Note:	for 1X clock with Intel SL Enhanced CPU(Central Processing Unit) The microprocessor which executes programs on your computer., bit 6 must be =1
SeeAlso: #P0135,#P0147,#P0148


Bitfields for 82C463MV PMU control 2 (doze timer, register 41h):
Bit(s)	Description	(Table P0147)
 7-5	hardware doze time-out selector
	101 512 ms
	110 2 sec
	111 8 sec
 4-2	hardware doze-mode CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock selector
	000 CPUCLK/1
	001 CPUCLK/2
	010 CPUCLK/4
	011 CPUCLK/8 (should be used during CPU(Central Processing Unit) The microprocessor which executes programs on your computer. stop clock only)
	100 CPUCLK/16 (should be used during CPU(Central Processing Unit) The microprocessor which executes programs on your computer. stop clock only)
	101 CPUCLK/3
	110 reserved
	111 reserved
 1	enable LCD_ACCESS, KBD_ACCESS, DSK_ACCESS access to auto trigger
	  the hardware doze timer
 0	disable hardware doze-mode (enable APM doze-mode support)
SeeAlso: #P0135,#P0146,#P0148


Bitfields for 82C463MV PMU control 3 (timers other than doze, register 42h):
Bit(s)	Description	(Table P0148)
 7-6	clock source for general-purpose timer
	00 SQW0
	01 SQW1
	10 SQW2
	11 SQW3
 5-4	clock source for keyboard timer (see bits 7-6)
 3-2	clock source for disk timer (see bits 7-6)
 1-0	clock source for LCD(Liquid Crystal Display) timer (see bits 7-6)
SeeAlso: #P0135,#P0147,#P0149


Bitfields for 82C463MV PMU control 4 (register 43h):
Bit(s)	Description	(Table P0149)
 7	disable monitoring of PORTIBM PC Portable (uses same BIOS as XT) 3B0h-3DFh
 6	disable monitoring of memory range A0000h-BFFFFh
 5-4	LOWBAT pin sample rate
	if register 40h bit 6 =1
	    00 32 seconds
	    01 64 seconds
	    10 128 seconds
	    11 reserved
	if register 40h bit 6	 =0
	    00 8 seconds
	    01 16 seconds
	    10 32 seconds
	    11 reserved
 3	reserved (0)
 2-0	ATIBM PC AT clock select
	000 OSCCLK2/8
	001 OSCCLK2/6
	010 OSCCLK2/4
	011 OSCCLK2/3
	100 OSC14/2 (7.2 MHz)
	111 stop
SeeAlso: #P0135,#P0146,#P0149,#P0150


Bitfields for 82C463MV GNR_ACCESS control, I/O base address line A9 (reg. 49h):
Bit(s)	Description	(Table P0150)
 7	GNR_ACCESS I/O base address bit A9
 6	enable compare in WRITE cycle
 5	enable compare in READ cycle
 4-0	I/O address A5-A1 mask bits. For each bit =1, the corresponding bit
	  in register 48h is not compared (this is used to determine I/O
	  address block size)
SeeAlso: #P0135,#P0149


Bitfields for 82C463MV CSG0# control and base address line A9 (register 4Bh):
Bit(s)	Description	(Table P0151)
 7	Programmable Chip Select 0 (CSG0#) - I/O base address line A9
 6	enable CSG0# for I/O write cycles
 5	enable CSG0# for I/O read cycles
 4	=1 CSG0# active before ALE
	=0 CSG0# active just like I/O command pulse
 3-0	I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
	  in register 4Ah (bits 4-1) is not compared (this is used to
	  determine I/O address block size)
SeeAlso: #P0135,#P0152


Bitfields for 82C463MV CSG1# control and base address line A9 (register 4Dh):
Bit(s)	Description	(Table P0152)
 7	Programmable Chip Select 1 (CSG1#) - I/O base address line A9
 6	enable CSG1# for I/O write cycles
 5	enable CSG1# for I/O read cycles
 4	=1 CSG1# active before ALE
	=0 CSG1# active just like I/O command pulse
 3-0	I/O address A4-A1 mask bits. For each bit =1, the corresponding bit
	in register 4Ch (bits 4-1) is not compared (this is used to
	determine I/O address block size)
SeeAlso: #P0135,#P0151


Bitfields for OPTi 82C463MV idle timer control (register 4Eh):
Bit	Description	(Table P0153)
 7	CSG1 access
 6	CSG0 access
 5	LPTAbbreviation for Line PrinTer. access (it refers to PORTIBM PC Portable (uses same BIOS as XT) 378h-37Fh, PORTIBM PC Portable (uses same BIOS as XT) 278h-27Fh and
	  PORTIBM PC Portable (uses same BIOS as XT) 3BCh-3BFh)
 4	COM access (it refers to PORTIBM PC Portable (uses same BIOS as XT) 3F8h-3FFh and PORTIBM PC Portable (uses same BIOS as XT) 2F8h-2FFh)
 3	GNR_ACCESS
 2	KBD_ACCESS
 1	DSK_ACCESS
 0	LCD_ACCESS
Note:	If a bit is =1, the corresponding access will reload IDLE_TIMER
	  otherwise not.
SeeAlso: #P0135


Bitfields for 82C463MV suspend/resume control (register 50h):
Bit	Description	(Table P0154)
 7	software generation of SMI (enabled by bit 7 of register 59h)
	  writing 1 asserts SMI to CPU(Central Processing Unit) The microprocessor which executes programs on your computer. to start SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. operation
	  writing 0 clears the SMI (the SMI routine must clear this bit)
 6	reserved (0)
 5	IRQ8 active level
	=1 high active
	=0 low active
 4	disable the internal 14.3MHz clock (to conserve power)
 3	start doze-mode / read DOZE_TIMER status
	write: start APM doze-mode
	    =1 start doze-mode (if register 40h bit 0 =1)
	    =0 no effect
	read: hardware DOZE_TIMER time-out status bit
	    =1 hardware DOZE_TIMER has timed out
	    =0 hardware DOZE_TIMER still counting
 2	Ready To Resume (RTR), read-only
 1	PMU mode (read-only)
	=1 suspend-mode still active
	=0 all other modes
 0	start suspend-mode (write only)
	=1 start suspend-mode
	=0 no effect
SeeAlso: #P0135,#P0146,#P0161


Bitfields for 82C463MV beeper/sequencer control (register 51h):
Bit(s)	Description	(Table P0155)
 7-2	sequencer base address translated-to A17-A12 (A19-A18 are always 1
	  during this operation)
 1-0	beeper control (independent from PORTIBM PC Portable (uses same BIOS as XT) 61h)
	if register 40h bit 6 =1
	    00 no action
	    01 1KHz
	    10 off
	    11 2KHz
	if register 40h bit 6 =0
	    00 no action
	    01 4KHz
	    10 off
	    11 8KHz
SeeAlso: #P0135,#P0146


Bitfields for 82C463MV PMU Periferal Power (PPWR) control 1 (register 54h):
Bit(s)	Description	(Table P0156)
 7-4	write mask of PPWR low nibble
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PPWR (low nibble)
SeeAlso: #P0135,#P0157


Bitfields for 82C463MV PMU Periferal Power (PPWR) control 2 (register 55h):
Bit(s)	Description	(Table P0157)
 7-4	write mask of PPWR high nibble
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PPWR (high nibble) (default =1)
SeeAlso: #P0135,#P0156


Bitfields for OPTi 82C463MV PIO control 1 (register 56h):
Bit(s)	Description	(Table P0158)
 7-4	write mask of PIO bits 3-0
	=1 enable write on corresponding bit
	=0 write disable
 3-0	read/write data bits for PIO
SeeAlso: #P0135,#P0159,#P0173


Bitfields for OPTi 82C463MV PIO control 2 (register 57h):
Bit	Description	(Table P0159)
 7	enable refresh (BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. must set this bit to 1 after power up)
 6	enable interrupts to generate PMI #6 (see also #P0167,#P0171)
 5	disable monitoring floppy drive accesses
 4	disable monitoring hard drive accesses
 3	PIO3/STPGNT# pin direction
	=1 output
	=0 input
 2	PIO2/CPUSPD pin direction (see bit 3)
 1	PIO1/NOWS# pin direction (see bit 3)
 0	PIO0 pin direction (see bit 3)
SeeAlso: #P0135,#P0158


Bitfields for OPTi 82C463MV PMU event control 1 (register 58h):
Bit(s)	Description	(Table P0160)
 7-6	LOWBAT PMI #3 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 5-4	EPMI2 PMI #2 configuration (see bits 7-6)
 3-2	EPMI1 PMI #1 configuration (see bits 7-6)
 1-0	LLOWBAT PMI #0 configuration (see bits 7-6)
SeeAlso: #P0135


Bitfields for OPTi 82C463MV PMU event control 2 (register 59h):
Bit(s)	Description	(Table P0161)
 7	global software SMI enable (see also bit 7 of register 50h at #P0154)
 6	reload timers during a resume sequence
 5-4	resume or INTR PMI #6 and Suspend PMI #7 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 3-2	R_TIMER PMI #5 configuration (see bits 5-4)
 1-0	IDLE_TIMER PMI #4 configuration (see bits 5-4)
SeeAlso: #P0135


Bitfields for OPTi 82C463MV PMU event control 3 (register 5Ah):
Bit(s)	Description	(Table P0162)
 7-6	GNR_TIMER time out PMI #11 and access PMI #15 configuration
	00 disable
	01 sequencer
	10 reserved
	11 SMI
 5-4	KBD_TIMER time out PMI #10 and access PMI #14 cfg (see bits 7-6)
 3-2	DSK_TIMER time out PMI #9 and access PMI #13 cfg (see bits 7-6)
 1-0	LCD_TIMER time out PMI #8 and access PMI #12 cfg (see bits 7-6)
SeeAlso: #P0135,#P0163


Bitfields for OPTi 82C463MV PMU event control 4 (register 5Bh):
Bit	Description	(Table P0163)
 7	IRQ15 SMI select
	=1 enable SMI select (SMI internally connected to IRQ15) and
	  disable IRQ15 hardware pin function
	=0 disable SMI select (enable IRQ15 pin function as normal)
 6	disable all SMI
 5	enable sequencer
 4	SMI Type
	=0 Intel style SMI (SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. identified by SMIACT#)
	=1 AMD DXLV or Cyrix style SMI (SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. identified by SMIADS#)
	Note:	for Intel-style SMI, the 3000h/4000h segments will relocate to
		  B000h/A000h when in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events.; for AMD/Cyrix, the 7000h/6000h
		  segments will relocate to B000h/A000h when in SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events.
 3	enable PMI source #15
 2	enable PMI source #14
 1	enable PMI source #13
 0	enable PMI source #12
SeeAlso: #P0135,#P0162,#P0164


Bitfields for OPTi 82C463MV SMI source (low) (register 5Ch):
Bit	Description	(Table P0164)
 7	PMI #7 - SUSPEND
 6	PMI #6 - RESUME or INTR
 5	PMI #5 - R_TIMER time out
 4	PMI #4 - IDLE_TIMER time out
 3	PMI #3 - LOWBAT pin
 2	PMI #2 - EPMI2 pin (external PMI source)
 1	PMI #1 - EPMI1 pin (external PMI source)
 0	PMI #0 - LLOWBAT pin
SeeAlso: #P0135,#P0165


Bitfields for OPTi 82C463MV SMI source (high) (register 5Dh):
Bit	Description	(Table P0165)
 7	PMI #15 - GNR_ACCESS
 6	PMI #14 - KBD_ACCESS
 5	PMI #13 - DSK_ACCESS
 4	PMI #12 - LCD_ACCESS
 3	PMI #11 - GNR_TIMER
 2	PMI #10 - KBD_TIMER
 1	PMI #9 - DSK_TIMER
 0	PMI #8 - LCD_TIMER
SeeAlso: #P0135,#P0164


Bitfields for OPTi 82C463MV clock stretching control (register 5Eh):
Bit	Description	(Table P0166)
 7	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock stretch memory code cycle
 6	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock stretch write cycle
 5	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock stretch read cycle
 4	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock stretch I/O cycle
 3	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock stretch memory data cycle
 2	enable stop ATCLK when not in ATIBM PC AT bus cycle
 1	ATCLK stretch
	=1 synchronous
	=0 asynchronous
 0	reserved (0)
SeeAlso: #P0135


Bitfields for OPTi 82C463MV resume interrupt control (register 5Fh):
Bit(s)	Description	(Table P0167)
 7	LCD_ACCESS includes ATIBM PC AT bus video access
 6	LCD_ACCESS includes Local bus video access
 5	enable all resume sources of register 6Ah (see also #P0176,#P0159)
 4	RI counter count out will generate resume
 3-0	number of RI counts
SeeAlso: #P0135


Bitfields for OPTi 82C463MV debounce control (register 61h):
Bit(s)	Description	(Table P0168)
 7-6	LOWBAT and LLOWBAT pin debounce rate select
	if register 40h bit 6 =1
	    00 no debounce
	    01 250 microseconds
	    10 8ms
	    11 500ms
	if register 40h bit 6 =0
	    00 no debounce
	    01 62.5 microseconds
	    10 2 ms
	    11 125 ms
 5-4	SUSP/RSM pin debounce rate select
	if register 40h bit 6 =1
	    00 reserved
	    01 latch high to low edge
	    10 4 ms (low to high)
	    11 8 ms (low to high)
	if register 40h bit 6 =0
	    00 reserved
	    01 latch high to low edge
	    10 1 ms (low to high)
	    11 2 ms (low to high)
 3	reserved (0)
 2	enable STPCLK protocol for switching CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock frequencies
 1-0	STPCLK# delay (for use when STPCLK protocol is enabled)
	00 no delay
	01 120 microseconds
	10 240 microseconds
	11 1ms, if register 40h bit 6 set; 240 microseconds if clear
SeeAlso: #P0135,#P0146


Bitfields for OPTi 82C463MV doze-mode IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (register 62h):
Bit	Description	(Table P0169)
 7	enable IRQ13
 6	enable IRQ8
 5	enable IRQ7
 4	enable IRQ12
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ0
Notes:	in hardware doze-mode the selected interrupts will be used to re-load
	  the hardware DOZE_TIMER and/or trigger the system out of doze-mode
	in APM doze-mode the selected interrupts will be used to trigger the
	  system out of doze-mode only
SeeAlso: #P0135,#P0172,#P0170


Bitfields for OPTi 82C463MV idle timer IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (register 63h):
Bit	Description	(Table P0170)
 7	enable EPMI1 (level trigger)
 6	enable IRQ13
 5	enable IRQ8
 4	enable IRQ7
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ0
SeeAlso: #P0135,#P0169,#P0171


Bitfields for OPTi 82C463MV PMI#6 IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (register 64h):
Bit	Description	(Table P0171)
 7	enable IRQ14
 6	enable IRQ8
 5	enable IRQ7
 4	enable IRQ6
 3	enable IRQ5
 2	enable IRQ4
 1	enable IRQ3
 0	enable IRQ1
Note:	the value written into this register selects which IRQs generate
	  PMI#6 in normal mode, the value read from this register indicates
	  active IRQs at the time of the read
SeeAlso: #P0135,#P0159,#P0170


Bitfields for OPTi 82C463MV doze-mode configuration (register 65h):
Bit	Description	(Table P0172)
 7	enable monitoring all interrupt signals during hw or sw doze-mode
 6	doze-mode STPCLK protocol selector (see also #P0168)
	=1 STPCLK will latch for stopping the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock (APM)
	     The delay is determined by register 61h bits 1-0
	=0 STPCLK will pulse for changing the frequency of the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock
	  (hw doze-mode).
	     The pulse width is determined by register 61h bits 1-0
 5	enable EPMI1 to reload hardware DOZE_TIMER and exit from hardware or
	  software doze-mode
 4	enable recognition of SMI during APM stop clock
 3	allow IRQ1 to exit from hw or sw doze-mode (write-only)
	(see also #P0169)
 2-0	reserved (0)
SeeAlso: #P0135,#P0173


Bitfields for OPTi 82C463MV suspend control (register 66h):
Bit	Description	(Table P0173)
 7	refresh type during suspend
	=1 self refresh
	=0 normal refresh (refresh rate selected by register 67h bit 6)
 6	KBCLK during suspend
	=1 16 KHz
	=0 7.16 MHz (14.318 MHz /2)
 5	software (APM) CPU(Central Processing Unit) The microprocessor which executes programs on your computer. stop-clock control
	=1 the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock can be stopped by entering APM doze-mode (that is
	  setting register 50h bit 3 to 1)
	=0 APM doze-mode will use the hw doze-mode clock selected by
	  bits 4-2 of register 41h
 4	avoid asserting HOLD before stopping the clock
 3	PIO3/STPGNT# pin selector
	=1 STPGNT# function (set register 57h bit 3 to input mode)
	    This is for use with CPUs that use the hw stop grant signal
	      to acknowledge stop request
	=0 PIO3 function (set register 57h bit 3 to determine input or
	  output mode)
 2	PIO2/CPUSPD pin selector
	=1 CPUSPD function, CPU(Central Processing Unit) The microprocessor which executes programs on your computer. speed indicator output (set register 57h
	  bit 2 to output mode)
	=0 PIO2 function (set register 57h bit 2 to determine input or
	  output mode)
 1	PIO1/NOWS# pin selector
	=1 NOWS# function (set register 57h bit 1 to input mode)
	=0 PIO1 function (set register 57h bit 1 to determine input or
	  output mode)
 0	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock change request protocol
Note:	for hardware doze mode, bit 5 must be 0
SeeAlso: #P0135,#P0147,#P0154,#P0159,#P0174


Bitfields for OPTi 82C463MV CPU(Central Processing Unit) The microprocessor which executes programs on your computer. frequency (register 67h):
Bit(s)	Description	(Table P0174)
 7	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock control during suspend
	=1 dynamic CPU(Central Processing Unit) The microprocessor which executes programs on your computer. (in suspend-mode, bits 2-0 select the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock)
	=0 static CPU(Central Processing Unit) The microprocessor which executes programs on your computer. (in suspend-mode, 82C463MV stops the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock)
 6	refresh control
	=1 slow refresh (128 ms)
	=0 normal refresh (15 ms for normal operation, 30 ms for suspend mode)
 5	PMU global enabler
 4	reserved (1)
 3	reserved (0)
 2-0	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock frequency
	000 CPUCLK/1
	001 CPUCLK/2
	010 CPUCLK/4
	101 CPUCLK/3
	else reserved
SeeAlso: #P0135


Bitfields for OPTi 82C463MV timer clock source (register 68h):
Bit(s)	Description	(Table P0175)
 7-6	R_TIMER clock source selector
	00 SQW0
	01 SQW1
	10 SQW2
	11 SQW3
 5-4	IDLE_TIMER clock source selector (see bits 7-6)
 3-2	resume recovery time
	if register 40h bit 6 =1
	    00 8 ms
	    01 32 ms
	    10 128 ms
	    11 256 ms
	if register 40h bit 6 =0
	    00 2 ms
	    01 8 ms
	    10 32 ms
	    11 64 ms
 1	enable PPWR bit 1 suspend auto toggle (see also #P0156)
 0	enable PPWR bit 0 suspend auto toggle (see also #P0156)
Note:	bits 1 and 0 are not influenced by mask bits 5 and 4 of register 54h
SeeAlso: #P0135,#P0146


Bitfields for OPTi 82C463MV resume IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. selects (register 6Ah):
Bit	Description	(Table P0176)
 7	enable EPMI2 (resume on a rising edge)
 6	enable EPMI1 (resume on a rising edge)
 5	enable IRQ8 (resume on a falling edge)
 4	enable IRQ7 (resume on a rising edge)
 3	enable IRQ5 (resume on a rising edge)
 2	enable IRQ4 (resume on a rising edge)
 1	enable IRQ3 (resume on a rising edge)
 0	enable IRQ1 (resume on a rising edge)
SeeAlso: #P0135


Bitfields for OPTi 82C463MV resume sources (register 6Bh):
Bit(s)	Description	(Table P0177)
 7	refresh pulse width during sequencer operation
	=1 6 ATIBM PC AT clocks
	=0 4 ATIBM PC AT clocks
 6-3	reserved (0)
 2-0	resume sources (read-only)
	001 RI
	010 INTR (as selected in register 6Ah)
	100 SUSP/RSM pin
	else reserved
SeeAlso: #P0135,#P0176
                                                                                

PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS
Desc:	The OPTi 486SXWB contains three chips and is designed for systems
	  running at 20, 25 and 33MHz.	The chipset includes an 82C493 System
	  Controller (SYSC), the 82C392 Data Buffer Controller, and the
	  82C206 Integrated peripheral Controller (IPC(Inter-Process Communication) Any one of numerous methods for allowing two or more separate processes to exchange data.).
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  configuration register index (see #P0178)
0024  RW  configuration register data


(Table P0178)
Values for OPTi 82C493 System Controller configuration register index:
 20h	Control Register 1 (see #P0179)
 21h	Control Register 2 (see #P0180)
 22h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control Register 1 (see #P0181)
 23h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control Register 2 (see #P0182)
 24h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Control Register 1 (see #P0183)
 25h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Control Register 2 (see #P0184)
 26h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control Register 3 (see #P0185)
 27h	Control Register 3 (see #P0186)
 28h	Non-cachable Block 1 Register 1 (see #P0187)
 29h	Non-cachable Block 1 Register 2 (see #P0188)
 2Ah	Non-cachable Block 2 Register 1 (see #P0187)
 2Bh	Non-cachable Block 2 Register 2 (see #P0188)


Bitfields for OPTi-82C493 Control Register 1:
Bit(s)	Description	(Table P0179)
 7-6	Revision of 82C493 (readonly) (default=01)
 5	Burst wait state control
	1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2
	0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default)
	(if bit 5 is set to 1, bit 4 must be set to 0)
 4	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. memory data buffer output enable control
	0 = disable (default)
	1 = enable
	(must be disabled for frequency <= 33Mhz)
 3	Single Address Latch Enable (ALE)
	0 = disable (default)
	1 = enable
	(if enabled, SYSC will activate single ALE rather than multiples
	  during bus conversion cycles)
 2	enable Extra ATIBM PC AT Cycle Wait State (default is 0 = disabled)
 1	Emulation keyboard Reset Control
	0 = disable (default)
	1 = enable
	Note:	This bit must be enabled in BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. default value; enabling this
		  bit requires HALT instruction to be executed before SYSC
		  generates processor reset (CPURST)
 0	enable Alternative Fast Reset (default is 0 = disabled)
SeeAlso: #P0180,#P0186


Bitfields for OPTi-82C493 Control Register 2:
Bit(s)	Description	(Table P0180)
 7	Master Mode Byte Swap Enable
	0 = disable (default)
	1 = enable
 6	Emulation Keyboard Reset Delay Control
	0 = Generate reset pulse 2us later (default)
	1 = Generate reset pulse immediately
 5	disable Parity Check (default is 0 = enabled)
 4	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Enable
	0 = CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. disabled and DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. burst mode enabled (default)
	1 = CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. enabled and DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. burst mode disabled
 3-2	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Size
	00  64KB (default)
	01  128KB
	10  256KB
	11  512KB
 1	Secondary CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Read Burst Cycles Control
	0 = 3-1-1-1 cycle (default)
	1 = 2-1-1-1 cycle
 0	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Write Wait State Control
	0 = 1 wait state (default)
	1 = 0 wait state
SeeAlso: #P0179,#P0186


Bitfields for OPTi-82C493 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control Register 1:
Bit(s)	Description	(Table P0181)
 7	ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs.(F0000h - FFFFFh) Enable
	0 = read/write on write-protected DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	1 = read from ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs., write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. (default)
 6	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at D0000h - EFFFFh Area
	0 = disable (default)
	1 = enable
 5	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at E0000h - EFFFFh Area
	0 = disable shadow RAM(Random Access Memory)	See also DRAM, SRAM. (default)
	    E0000h - EFFFFh ROM(Read-Only Memory) A memory for program storage which may not be changed by the program as it runs. is defaulted to reside on XD bus
	1 = enable shadow RAM(Random Access Memory)	See also DRAM, SRAM.
 4	enable write-protect for Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at D0000h - DFFFFh Area
	0 = disable (default)
	1 = enable
 3	enable write-protect for Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at E0000h - EFFFFh Area
	0 = disable (default)
	1 = enable
 2	Hidden refresh enable (with holding CPU(Central Processing Unit) The microprocessor which executes programs on your computer.)
	(Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. are used)
	1 = disable (default)
	0 = enable
 1	unused
 0	enable Slow RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading.  The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors.   See also DRAM. (four times slower than normal refresh)
	(default is 0 = disable)
SeeAlso: #P0182


Bitfields for OPTi-82C493 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control Register 2:
Bit(s)	Description	(Table P0182)
 7	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at EC000h - EFFFFh area
 6	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at E8000h - EBFFFh area
 5	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at E4000h - E7FFFh area
 4	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at E0000h - E3FFFh area
 3	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at DC000h - DFFFFh area
 2	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at D8000h - DBFFFh area
 1	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at D4000h - D7FFFh area
 0	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at D0000h - D3FFFh area
Note:	the default is disabled (0) for all areas


Bitfields for OPTi-82C493 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Control Register 1:
Bit(s)	Description	(Table P0183)
 7	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. size
	0 = 256K DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. mode
	1 = 1M and 4M DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. mode
 6-4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. types used for bank0 and bank1
	bits 7-4  Bank0	  Bank1
	0000	  256K	     x
	0001	  256K	  256K
	0010	  256K	    1M
	0011	     x	     x
	01xx	     x	     x
	1000	    1M	     x	(default)
	1001	    1M	    1M
	1010	    1M	    4M
	1011	    4M	    1M
	1100	    4M	     x
	1101	    4M	    4M
	111x	     x	     x
 3	unused
 2-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. types used for bank2 and bank3
	bits 7,2-0  Bank2  Bank3
	x000	   1M	    x
	x001	   1M	   1M
	x010	    x	    x
	x011	   4M	   1M
	x100	   4M	    x
	x101	   4M	   4M
	x11x	    x	    x  (default)
SeeAlso: #P0184


Bitfields for OPTi-82C493 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Control Register 2:
Bit(s)	Description	(Table P0184)
 7-6	Read cycle additional wait states
	00 not used
	01 = 0
	10 = 1
	11 = 2 (default)
 5-4	Write cycle additional wait states
	00 = 0
	01 = 1
	10 = 2
	11 = 3 (default)
 3	Fast decode enable
	0 = disable fast decode. DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. base wait states not changed (default)
	1 = enable fast decode. DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. base wait state is decreased by 1
	Note:	This function may be enabled in 20/25Mhz operation to speed up
		  DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. access.	If bit 4 of index register 21h (cache enable
		  bit) is enabled, this bit is automatically disabled--even if
		  set to 1
 2	unused
 1-0	ATCLK selection
	00  ATCLK = CLKI/6 (default)
	01  ATCLK = CLKI/4 (default)
	10  ATCLK = CLKI/3
	11  ATCLK = CLK2I/5  (CLKI * 2 /5)
	Note:	bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be
		  set to 0 when 82C493 is reset.
SeeAlso: #P0183,#P0185


Bitfields for OPTi-82C493 Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control Register 3:
Bit(s)	Description	(Table P0185)
 7	unused
 6	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. copy enable for address C0000h - CFFFFh
	0 = Read/write at ATIBM PC AT bus (default)
	1 = Read from ATIBM PC AT bus and write into shadow RAM(Random Access Memory)	See also DRAM, SRAM.
 5	Shadow write protect at address C0000h - CFFFFh
	0 = Write protect disable (default)
	1 = Write protect enable
 4	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C0000h - CFFFFh
 3	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at CC000h - CFFFFh
 2	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C8000h - CBFFFh
 1	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C4000h - C7FFFh
 0	enable Shadow RAM(Random Access Memory)	See also DRAM, SRAM. at C0000h - C3FFFh
Note:	the default is disabled (0) for bits 4-0
SeeAlso: #P0183,#P0184


Bitfields for OPTi-82C493 Control Register 3:
Bit(s)	Description	(Table P0186)
 7	enable NCA# pin to low state (default is 1 = enabled)
 6-5	unused
 4	Video BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. at C0000h - C8000h non-cacheable
	0 = cacheable
	1 = non-cacheable (default)
 3-0	Cacheable address range for local memory
	0000  0 - 64MB
	0001  0 - 4MB (default)
	0010  0 - 8MB
	0011  0 - 12MB
	0100  0 - 16MB
	0101  0 - 20MB
	0110  0 - 24MB
	0111  0 - 28MB
	1000  0 - 32MB
	1001  0 - 36MB
	1010  0 - 40MB
	1011  0 - 44MB
	1100  0 - 48MB
	1101  0 - 52MB
	1110  0 - 56MB
	1111  0 - 60MB
	Note:	If total memory is 1MB or 2MB the cacheable range is 0-1 MB or
		  0-2 MB and independent of the value of bits 3-0
SeeAlso: #P0179,#P0180


Bitfields for OPTi-82C493 Non-cacheable Block Register 1:
Bit(s)	Description	(Table P0187)
 7-5	Size of non-cachable memory block
	000  64K
	001  128K
	010  256K
	011  512K
	1xx  disabled (default)
 4-2	unused
 1-0	Address bits 25 and 24 of non-cachable memory block (default = 00)
Note:	this register is used together with configuration register 29h
	  (non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to
	  define a non-cacheable block.	 The starting address must be a
	  multiple of the block size
SeeAlso: #P0178,#P0188


Bitfields for OPTi-82C493 Non-cacheable Block Register 2:
Bit(s)	Description	(Table P0188)
 7-0	Address bits 23-16 of non-cachable memory block (default = 0001xxxx)
Note:	the block address is forced to be a multiple of the block size by
	  ignoring the appropriate number of the least-significant bits
SeeAlso: #P0178,#P0187
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi "Viper" (82C557) CHIPSET - SYSTEM CONTROL REGISTERS
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0189)
0023  RW  DMAsee Direct Memory Access clock select (see #P0087)
0024  RW  chip set data


(Table P0189)
Values for OPTi "Viper" (82C557) system control registers:
 00h	Byte Merge/Prefetch and Sony CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Module Control register (see #P0190)
 00h	Compatible DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Configuration register 1 (see #P0191) (refer to note)
 01h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Control register 1 (see #P0192)
 02h	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register 1 (see #P0193)
 03h	CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register 2 (see #P0194)
 04h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control register 1 (see #P0195)
 05h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control register 2 (see #P0197)
 06h	Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control register 3 (see #P0198)
 07h	Tag Test register (see #P0199)
 08h	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register (see #P0200)
 09h	System Memory Function register (see #P0201)
 0Ah	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole A Address Decode register 1 (see #P0202)
 0Bh	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole B Address Decode register 2 (see #P0203)
 0Ch	Extended DMAsee Direct Memory Access register (see #P0204)
 0Dh	Clock Control register (see #P0205)
 0Eh	Cycle Control register 1 (see #P0206)
 0Fh	Cycle Control register 2 (see #P0207)
 10h	Miscellaneous Control register 1 (see #P0208)
 11h	Miscellaneous Control register 2 (see #P0209)
 12h	RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading.  The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors.   See also DRAM. Control register (see #P0210)
 13h	Memory Decode Control register 1 (see #P0211)
 14h	Memory Decode Control register 2 (see #P0213)
 15h	PCI Cycle Control register 1 (see #P0214)
 16h	Dirty/Tag RAM(Random Access Memory)	See also DRAM, SRAM. Control register (see #P0215)
 17h	PCI Cycle Control register 2 (see #P0216)
 18h	Tristate Control register (see #P0217)
 19h	Memory Decode Control register 3 (see #P0218)
 1Ah-1Fh reserved
Note:	Byte Merge/Prefetch and Sony CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Module Control register is accessed
	  through register 00h when bit 7 of register 13h is set, otherwise
	  Compatible DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Configuration register 1 is accessed as register 00h
	reserved registers 1Ah-1Fh must be written to 0
SeeAlso: #P0121,#P0211


Bitfields for OPTi "Viper" Byte Merge / Sony CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Module Control register:
Bit(s)	Description	(Table P0190)
 7	enable pipelining of single CPU(Central Processing Unit) The microprocessor which executes programs on your computer. cycles to memory
 6	enable video memory byte/word read prefetch. Enables the prefetching
	  of bytes/words from PCI video memory to the CPU(Central Processing Unit) The microprocessor which executes programs on your computer.
 5	enable Sony SONIC-2WP support. If set, the ensure that the L2 cache
	  has been disabled (register 02h bits 3-2)
 4	enable byte/word merge support
 3	enable byte/word merging with CPU(Central Processing Unit) The microprocessor which executes programs on your computer. pipelining (NA# generation) support
 2-1	time-out counter for byte/word merge. Determines the maximum time
	  difference between two consecutive PCI bye/word writes to allow
	  merging
	00  4 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. CLKs
	01  8 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. CLKs
	10 12 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. CLKs
	11 16 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. CLKs
 0	enable internal hold requests to be blocked while performing byte merge
SeeAlso: #P0189


Bitfields for OPTi "Viper" Compatible DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Configuration register 1:
Bit(s)	Description	(Table P0191)
 7	enable pipelining of single CPU(Central Processing Unit) The microprocessor which executes programs on your computer. cycles to memory
 6	second bank SIMM selection. SIMMs need to be single sided
	0 single sided SIMM not installed in bank 0
	1 single sided SIMM installed in bank 0
 5	first bank SIMM selection. SIMMs need to be single sided
	0 single sided SIMM not installed in bank 0
	1 single sided SIMM installed in bank 0
 4-0	banks 0 thru 3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration
	(val)	Bank0	Bank1	Bank2	Bank3
	00000	256K	256KB	-	-
	00001	512K	512K	-	-
	00010	1M	1M	-	-
	00011	2M	2M	-	-
	00100	4M	4M	-	-
	00101	8M	8M	-	-
	00110	256K	256K	256K	256K
	00111	256K	256K	512K	512K
	01000	512K	512K	512K	512K
	01001	256K	256K	1M	1M
	01010	512K	512K	1M	1M
	01011	1M	1M	1M	1M
	01100	256K	256K	2M	2M
	01101	512K	512K	2M	2M
	01110	1M	1M	2M	2M
	01111	2M	2M	2M	2M
	10000	256K	256K	4M	4M
	10001	512K	512K	4M	4M
	10010	1M	1M	4M	4M
	10011	2M	2M	4M	4M
	10100	4M	4M	4M	4M
	10101	256K	256K	8M	8M
	10110	512K	512K	8M	8M
	10111	1M	1M	8M	8M
	11000	2M	2M	8M	8M
	11001	4M	4M	8M	8M
	11010	8M	8M	8M	8M
Note:	these settings maintain backward compatibility with the "Python"
	  (82C546/82C547) chipset, and they do not allow for much flexibility
SeeAlso: #P0189


Bitfields for OPTi "Viper" (82C557) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Control register 1:
Bit(s)	Description	(Table P0192)
 7	row address hold after RAS# active in CLKs
	0 2 CLKs
	1 1 CLK
 6	RAS# active/inactive on entering master mode
	0 normal page mode when starting a master cycle, RAS# will remain
	1 RAS# inactive when starting a master cycle
 5-4	RAS pulse width used during refresh
	00 7 CLKs
	01 6 CLKs
	10 5 CLKs
	11 4 CLKs
 3	CASsee Communicating Applications Specification pulse width during reads
	0 3 CLKs
	1 2 CLKs
 2	CASsee Communicating Applications Specification pulse width during writes 
	0 3 CLKs
	1 2 CLKs
 1-0	RAS precharge time
	00 6 CLKs
	01 5 CLKs
	10 4 CLKs
	11 3 CLKs
SeeAlso: #P0189,#P0193,#P0219


Bitfields for OPTi "Viper" (82C557) CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register 1:
Bit(s)	Description	(Table P0193)
 7-6	cache size selection; determines size of the L2 cache, along with
	  register 0Fh bit 0. When set, it works as a *16 multiplier
	00 (Viper)  64K (1M when register 0Fh bit 0 set)
	   (Vendetta) reserved
	01 (Viper) 128K (2M when register 0Fh bit 0 set)
	   (Vendetta) reserved
	10 256K (reserved when register 0Fh bit 0 set)
	11 512K (reserved when register 0Fh bit 0 set)
 5-4	cache write policy; determines the write policy for the L2 cache
	00 L2 cache write-through
	01 Adaptive Write-back Mode 1
	10 Adaptive Write-back Mode 2
	11 L2 cache write-back
 3-2	cache mode select; determines the operating mode of the L2 cache
	00 disable
	01 Test Mode 1, External Tag Write (Tag data write-through reg. 07h)
	10 Test Mode 2, External Tag Read (Tag data read from register 07h)
	11 enable L2 cache
 1	enable DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. posted write
 0	CASsee Communicating Applications Specification precharge time
	0 2 CLKs
	1 1 CLK
SeeAlso: #P0189,#P0199,#P0207,#P0194,#P0219


Bitfields for OPTi "Viper" (82C557) CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register 2:
Bit(s)	Description	(Table P0194)
 7-6	L2 cache write burst mode timings
	00 X-4-4-4
	01 X-3-3-3
	10 X-2-2-2
	11 X-1-1-1
 5-4	L2 cache write lead-off cycle timings
	00 5-X-X-X
	01 4-X-X-X
	10 3-X-X-X
	11 2-X-X-X
 3-2	L2 cache read burst mode timings
	00 X-4-4-4
	01 X-3-3-3
	10 X-2-2-2
	11 X-1-1-1
 1-0	L2 cache read lead-off cycle timings
	00 5-X-X-X
	01 4-X-X-X
	10 3-X-X-X
	11 2-X-X-X
Note:	SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. double bank implementation does not support lead-off timing
SeeAlso: #P0189,#P0193,#P0219


Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control register 1:
Bit(s)	Description	(Table P0195)
 7-6	CC000-CFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
 5-4	C8000-CBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
 3	enable synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. pipelined read cycle 1-1-1-1
 2	E0000-EFFFF range selection
	0 area will always be non-cacheable
	1 are will be treated like the F0000h BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. area
 1-0	C0000-C7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
Note:	bit 3 will act only when register 11h bit 3 and register 03h bits 3-2
	  are all set
	when bit 2 is set, register 06h bits 3-0 should be set identically
SeeAlso: #P0189,#P0197,#P0219


(Table P0196)
Values for OPTi "Viper"/"Vendetta" Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control setting:
 00	read/write PCI bus
 01	read from DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM./write to PCI
 10	read from PCI/write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
 11	read from/write to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
SeeAlso: #P0195,#P0197,#P0198,#P0219


Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control register 2:
Bit(s)	Description	(Table P0197)
 7-6	DC000-DFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
 5-4	D8000-DBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
 3-2	D4000-D7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
 1-0	D0000-D3FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
SeeAlso: #P0189,#P0195,#P0198,#P0219


Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM(Random Access Memory)	See also DRAM, SRAM. Control register 3:
Bit(s)	Description	(Table P0198)
 7	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. hole in system memory from 80000-9FFFF; gives the user the option
	  to have some other device in this address range instead of system
	  memory. When set, the SYSC will not start the system DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. controller
	  for accesses to this particular address range
	0 no memory hole
	1 enable memory hole
 6	wait state addition for PCI master snooping
	0 do not add a wait state
	1 add a wait state for the cycle access to finish and then do snooping
 5	enable C0000-C7FFF cacheability in L1 and L2 cache memory
 4	enable F0000-FFFFF cacheability in L1 and L2 cache memory
 3-2	F0000-FFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
 1-0	E0000-EFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM. (see #P0196)
Note:	L1 cacheability can be disabled thru register 08h bit 0
	If register 04h bit 2 is set, then F0000-FFFFF and E0000-EFFFF R/W
	control settings should have similar values
SeeAlso: #P0189,#P0197,#P0219


Bitfields for OPTi "Viper"/"Vendetta" Tag Test register:
Bit(s)	Description	(Table P0199)
 7-0	Tag Test register; when in cache Test Mode, data is read from/written
	  to this register
SeeAlso: #P0189,#P0193,#P0219


Bitfields for OPTi "Viper"/"Vendetta" CPU(Central Processing Unit) The microprocessor which executes programs on your computer. CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Control register:
Bit(s)	Description	(Table P0200)
 7	L2 cache single/double bank select
	0 (Viper) two banks of L2 cache
	  (Vendetta) reserved
	1 single bank of L2 cache (non-interleaved)
 6	enable snoop filtering for bus masters
 5	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. HITM# pin sample timing
	0 (Viper) delay one clock, therefore HITM# sampled on the third rising
	    edge of LCLK after EADS# has been asserted
	  (Vendetta) reserved
	1 do not delay, therefore HITM# sampled on the second rising edge
 4	enable parity checking
 3	Tag/Dirty RAM(Random Access Memory)	See also DRAM, SRAM. implementation
	0 (Viper) Tag and Dirty are on separate chips
	  (Vendetta) reserved
	1 Tag and Dirty are on the same chip
 2	enable CPU(Central Processing Unit) The microprocessor which executes programs on your computer. address pipelining
 1	enable L1 cache write-back and write-through control
	0 write-through only
	1 write-back enabled
 0	disable BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. and Video BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. areas cacheability in L1 cache
Notes:	If asynchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM., then cache memory banks (when two are present)
	  are interleaved, otherwise, they are not
	When register 04h bit 2 is set, bit 0 affects BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. area
	  E0000-EFFFF; when clear, bit 0 affects area F0000-FFFFF
SeeAlso: #P0189,#P0201,#P0219


Bitfields for OPTi "Viper" (82C557) System Memory Function register:
Bit(s)	Description	(Table P0201)
 7-6	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole B size
	(address specified by register 0Bh, and register 0Ch bits 3-2)
	00 512K
	01   1M
	10   2M
	11   4M
 5-4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole B control mode
	00 disable
	01 write-through for L1 and L2 cache
	10 non-cacheable for L1 and L2 cache
	11 enable hole in DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
 3-2	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole A size (settings same as bits 7-6)
	(address specified by register 0Ah, and register 0Ch bits 1-0)
 1-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole A control mode (settings same as bits 5-4)
SeeAlso: #P0189,#P0203,#P0204,#P0219


Bitfields for OPTi "Viper" (82C557) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole A Address Decode register 1:
Bit(s)	Description	(Table P0202)
 7-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole A address, bits 26-19
	(bits 1-0 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P0189,#P0204,#P0203,#P0219


Bitfields for OPTi "Viper" (82C557) DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole B Address Decode register 2:
Bit(s)	Description	(Table P0203)
 7-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole B address, bits 26-19
	(bits 3-2 of register 0Ch map onto bits 28-27 of HA lines)
SeeAlso: #P0189,#P0204,#P0202,#P0219


Bitfields for OPTi "Viper" (82C557) Extended DMAsee Direct Memory Access register:
Bit(s)	Description	(Table P0204)
 7	reserved (0)
 6	Fast BRDY# generation for DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. write page hits
	0 BRDY# for DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. writes generated on the fourth clock
	1 BRDY# for DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. writes generated on the third clock
 5	(Viper) HACALE one-half a clock cycle earlier
	    0 HACALE normal timing
	    1 HACALE one-half a clock cycle early enabled
	(Vendetta) reserved
 4	(Viper) wider cache WE# pulse
	    0 cache WE# pulse width is normal (~15ns)
	    1 cache WE# pulse is wider (~17.5ns)
	(Vendetta) reserved
 3-2	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole B starting address, bits 28-27 (see also #P0202)
 1-0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Hole A starting address, bits 28-27 (see also #P0203)
Note:	bits 26-19 of memory holes A and B are mapped from Indices 0Ah and 0Bh
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) Clock Control register:
Bit(s)	Description	(Table P0205)
 7	(Viper) clock source for generation the syncronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. timing
	    0 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock is the source for the timing and control signals
	    1 ECLK is the source for the timing and control signals
	(Vendetta) reserved (1)
 6	(Viper) this bit is set if the skew between ECLK and CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock is too
	  large (read-only bit, set by the 82C557 chip)
	(Vendetta) reserved (read-only)
 5	(Viper) enable auto skew detect; when this bit is set, bit 4 will be
	  set automatically if the skew between CLK and ECLK is too large
	(Vendetta) BRDY# PCI-to-ISA bridge request remove BOFF# disable
 4	(Viper) ECLK - CLK skew, activated when synchronou SRAMs are being used
	    0 skew between CLK and ECLK is not too large
	    1 skew is too large
	(Vendetta) 
	    0 preemption when CPU(Central Processing Unit) The microprocessor which executes programs on your computer. needs memory
	    1 reserved
 3	enable A0000-BFFFF as system memory
 2	wait state addition for PCI master doing address toggling as a 486
	0 linear burst mode style address toggling - no wait state addition
	1 i486 burst style address toggling - one wait state needs to be added
 1	(Viper) PCI cycle claimed by the 82C557 during PCI pre-snoop cycle
	    0 82C557 does not claim the PCI cycle after it asserts STOP#
	    1 82C557 claims the PCI cycle after it asserts STOP#
	(Vendetta) reserved
 0	slow CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock; should be set if the CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock frequency has been
	  reduced
	    0 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock frequency is normal
	    1 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock has been slowed down
	(Vendetta) reserved
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) Cycle Control register 1:
Bit(s)	Description	(Table P0206)
 7-6	(Viper) PCI master read burst wait state control
	    00 4 cycles
	    01 3 cycles
	    10 2 cycles
	    11 reserved
	(Vendetta) reserved
 5-4	(Viper) PCI master write burst wait state control (same settings as
	  bits 7-6)
	(Vendetta) reserved
 3	master cycle parity enable; this bit becomes applicable when bit 4 of
	  register 08h is set
	0 enable parity check during master cycles
	1 disable parity check during master cycles
 2	(Viper) HACALE timing control
	    0 HACALE high during HITM# before CPU(Central Processing Unit) The microprocessor which executes programs on your computer. ADS#
	    1 HACALE low and CA4 always enabled during HITM cycle
	(Vendetta) fast NA# generation enable
 1	enable write protection for L1 BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware.  The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
 0	PCI line comparator; this bit is only valid when bit 6 of register 08h
	  is set
	0 use line comparator in PCI master
	1 generate inquire cycle for every new FRAME#
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) Cycle Control register 2:
Bit(s)	Description	(Table P0207)
 7	enable PCI pre-snooping feature
 6	(Viper) ATIBM PC AT master wait state control
	    0 do not add any wait states for ATIBM PC AT master cycles
	    1 add wait wait states for ATIBM PC AT master cycles
	(Vendetta) ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. master access wait states enable (use if PCICLK <33MHz)
 5	(Viper) wait state addition for synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. even byte access
	    0 do not add a wait state for a synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. even byte access
	    1 add one wait state for a synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. even byte access
	(Vendetta) L2 write-through mode CPU-to-DRAM deep buffer enable
 4	PCI wait state addition for synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. L2 cache implementation
	0 master does not wait for end of current cycle + CPU-PCI clock to
	  become synchronous
	1 master waits for end of current cycle + wait for CPU-PCI clock to
	  become synchronous
 3	(Viper) reserved
	(Vendetta) L2 single cycle write hit when line already dirty
	    0 = 5 CLKs
	    1 = 3 CLKs
 2	(Viper) ADSC# generation for synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. read cycle
	    0 generate ADSC# immediately after CPU(Central Processing Unit) The microprocessor which executes programs on your computer. ADS# goes active
	    1 generate ADSC# one clock after CPU(Central Processing Unit) The microprocessor which executes programs on your computer. ADS# goes active
	(Vendetta) CPU(Central Processing Unit) The microprocessor which executes programs on your computer. to L2 cache hit cycle chipset ADSC# generation disable
 1	(Viper) reserved
	(Vendetta) two-PCI master fix
	    0 revision 2.0
 0	L2 cache size selector; works along with bits 1-0 of register 02h
	0 below 1M
	1 1M and above (Viper only)
SeeAlso: #P0189,#P0193,#P0219


Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 1:
Bit(s)	Description	(Table P0208)
 7	(Viper) early decode of PCI/VL/ATIBM PC AT cycle
	(Vendetta) early decode of PCI/ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. cycle
	0 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. to <bus> slave cycle triggered after second T2
	1 CPU(Central Processing Unit) The microprocessor which executes programs on your computer. to <bus> slave cycle triggered after first T2
 6	(Viper) cache modified write cycle timing
	    0 use the old address changing method, as in the 82C546/82C547
	    1 two bank cache, CA4 delayed one-half a clock for write cycles
	(Vendetta) reserved
 5	pipelined read cycle timing; determines the lead-off cycle
	0 3-X-X-X read followed by a 3-X-X-X piped read cycle
	1 3-X-X-X read followed by a 2-X-X-X piped read cycle
 4	(Viper) enable write hit pipelined
	    0 do not enable 2-X-X-X pipelined write hit cycles
	    1 enable 2-X-X-X pipelined write hit cycles
	(Vendetta) reserved
 3	(Viper) write pulse timing control for cache write hit cycles
	    0 do not change the write pulse timing during X-2-2-2 write hit
	      cycles
	    1 move the write pulse one-half a clock later in X-2-2-2 write hit
	      cycles
	(Vendetta) reserved
 2	(Viper) write pulse timing control for cache write hit cycles
	    0 do not change the write pulse timing during 3-X-X-X write hit
	      cycles
	    1 move the write pulse one-half a clock later in 3-X-X-X write hit
	      cycles
	(Vendetta) reserved
 1	(Viper) external 74F126 select
	    0 an external 74F126 is installed for CA3 and CA4
	    1 an external 74F126 is not installed for CA3 and CA4
	(Vendetta) reserved (1)
 0	LCLK select control; when this bit is set, the timing constraints
	  between the LCLK and the CPUCLK inputs to the SYSC need to be met.
	  This constraints are: LCLK <= 1/2 CPUCLK period before CPUCLK, and
	  LCLK <= 0.5ns after CPUCLK
	0 LCLK is asynchronous to the CPUCLK
	1 LCLK is synchronous to the CPUCLK; LCLK = CPUCLK/2
Note:	bit 1 should always be set to 1
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) Miscellaneous Control register 2:
Bit(s)	Description	(Table P0209)
 7-6	reserved; must be set to 0
 5	cache inactive during Idle state control
	0 SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. always active
	1 SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. inactive during Idle state (Viper only)
 4	next address (NA#) mode control
	0 normal NA# timing used with asynchronous SRAMs
	1 new NA# timing for synchronous SRAMs; used only when CPU(Central Processing Unit) The microprocessor which executes programs on your computer. operating
	  at 50MHz
 3	SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. type
	0 asynchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. (Viper only)
	1 synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM.
 2	(Viper) enable page miss posted write
	(Vendetta) reserved
 1	(Viper) ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA./DMAsee Direct Memory Access IOCHRDY control
	    0 old mode, no IOCHRDY during line hit
	    1 drive IOCHRDY low until cycle is finished
	(Vendetta) reserved
 0	(Viper) delay start
	    0 old mode, do not delay internal master cycle after an inquire
	      cycle
	    1 delay internal master cycles by one LCLK after an inquire cycle
	(Vendetta) reserved
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading.  The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors.   See also DRAM. Control register:
Bit(s)	Description	(Table P0210)
 7	REFRESH#/32KHz source selection
	0 REFRESH# source is REFRESH# pulse from the 82C558 or the ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. master
	1 REFRESH# pulse source is a 32KHz clock
 6	reserved; must be written to 0
 5-4	suspend mode refresh
	00 from CLK state machine
	01 slef refresh based on 32KHz only
	10 normal refresh based on 32KHz only
	11 undefined
 3-2	slow refresh
	00 refresh on every REFRESH#/32KHz falling edge
	01 refresh on alternate REFRESH#/32KHz falling edge
	10 refresh on one in four REFRESH#/32KHz falling edge
	1 refresh on every REFRESH#/32KHz toggle
 1	enable bits 23-17 of LA from RefreshThe process of periodically rewriting the contents of a DRAM memory chip to keep it from fading.  The term "refresh" is also commonly applied to redrawing the image on a CRT's phosphors.   See also DRAM. Page register (8Fh) during refresh
 0	enable output of bits 7-4 of DBC MP during master write
	0 disable the DBC from generation the MP[7:4] lines during PCI master
	  writes; there must be a pull-up on MP0
	1 enable the DBC to generate the MP[7:4] lines during PIC master
	  writes; there must be a pull-down on MP0
SeeAlso: #P0189,#P0211


Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 1:
Bit(s)	Description	(Table P0211)
 7	(Viper) memory decode select
	0 Byte Merge/Prefetch and Sony CacheCaching is a method of increasing performance by keeping frequently-used data in a location which is more quickly accessed. The most common caches are disk caches (store disk sectors in RAM) and RAM caches (store portions of main memory in special high-speed RAM which may be accessed as fast as the CPU is capable of accessing memory). See also Delayed Write, Write-Through. Module Control register is
	  available in register 00h; compatible to 82C547 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configurations
	1 Compatible DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. Configuration register is available in register 00h;
	  full decode option; this gives the user maximum flexibility in
	  choosing different DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configurations
	(Vendetta) reserved (1)
 6-4	full decode for logical bank 1 (RAS#1), if bit 7 set. This settings
	  apply to 36-pin banks only (see #P0212)
 3	enable SMRAM
 2-0	full decode for logical bank 0 (RAS#0), if bit 7 set. This settings
	  apply to 36-pin banks only (see #P0212)
SeeAlso: #P0189,#P0190,#P0191,#P0219


(Table P0212)
Values for OPTi "Viper" (82C557) Memory Bank Decode Control registers:
 000	  0K
 001	256K
 010	512K
 011	  1M
 100	  2M
 101	  4M
 110	  8M
 111	 16M
SeeAlso: #P0211,#P0213,#P0216


Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 2:
Bit(s)	Description	(Table P0213)
 7	(Viper) reserved; must be written to 0
	(Vendetta) reserved (1)
 6-4	full decode for logical bank 3 (RAS#3), if register 13h bit 7 is set
	  (see #P0212)
 3	SMRAM control
	0 disable SMRAM (enable SMRAM for both Code and Data if SMIACT# is
	  active and register 13h bit 3 is set)
	1 enable SMRAM (enable SMRAM for Code only if SMIACT# is active and
	  register 13h bit 3 is set)
 2-0	full decode for logical bank 2 (RAS#2), if register 13h bit 7 is set
	  (see #P0212)
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) PCI Cycle Control register 1:
Bit(s)	Description	(Table P0214)
 7-6	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. master to PCI memory slave, write IRDY# control
	00 3 LCLKs after end of address phase
	01 2 LCLKs after end of address phase
	10 1 LCLK after end of address phase
	11 0 LCLK after end of address phase
 5-4	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. master to PCI slave write posting, bursting control
	00 PCI slave write, no posting, no bursting
	01 PCI slave write, posting enabled, no bursting
	10 PCI slave write, posting enabled, conservative bursting
	11 PCI slave write, posting enabled, aggressive bursting
 3-2	master retry timer
	00 retries unmasked after 10 PCICLKs
	01 retries unmasked after 18 PCICLKs
	10 retries unmasked after 34 PCICLKs
	11 retries unmasked after 66 PCICLKs
 1	reserved; must be written to 0
 0	PCI cycle, FRAME# timing control for pipelined cycles
	0 PCI cycle FRAME# assertion is done in the conservative mode style
	1 PCI cycle FRAME# assertion is done in the aggressive mode style
SeeAlso: #P0189,#P0216,#P0219


Bitfields for OPTi "Viper"/"Vendetta" Dirty/Tag RAM(Random Access Memory)	See also DRAM, SRAM. Control register:
Bit(s)	Description	(Table P0215)
 7	(Viper) Dirty pin selection; reflects the kind of SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. chosen to
	  implement the Dirty RAM(Random Access Memory)	See also DRAM, SRAM.; it also determines the functionality of the
	  DIRTYI pin of the 82C557
	    0 DIRTYI pin is input-only
	    1 DIRTYI pin is bidirectional
	(Vendetta) reserved (1)
 6	reserved; must be written to 0
 5	Tag RAM(Random Access Memory)	See also DRAM, SRAM. size
	0 = 8-bit Tag (Viper only)
	1 = 7-bit Tag
 4	write hit cycle lead-off time when combining Dirty/Tag RAM(Random Access Memory)	See also DRAM, SRAM.
	0 single write hit lead-off cycle = 5 cycles
	1 single write hit lead-off cycle = 4 cycles
 3	pre-snoop control
	0 pre-snoop for starting address 0 only
	1 pre-snoop for all addresses except those on the line boundary
 2	(Viper) reserved; must be written to 0
	(Vendetta) synchronization between LCLK and CLK
	    0 LCLK is asynchronous to CLK
	    1 LCLK is synchronous to CLK
 1	(Viper) CPU(Central Processing Unit) The microprocessor which executes programs on your computer. to VL read access, DBC DLE# bits 1-0 timing
	    0 LCLK high
	    1 LCLK low
	(Vendetta) reserved
 0	(Viper) HDOE# timing control
	    0 HDOE# is negated normally
	    1 HDOE# is negated one clock before the cycle finishes
	(Vendetta) reserved
Note:	(Vendetta) bit 4 should be set same as register 22h bit 0
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper"/"Vendetta" PCI Cycle Control register 2:
Bit(s)	Description	(Table P0216)
 7	(Vipder) NA# assertion control for PCI slave accesses when synchronous
	  PCI clock is used
	    0 no pipelining for accesses to PCI slave
	    1 pipelining enabled for accesses to PCI slave for both synchronous
	      and asynchronous PCI solutions; if set, overrides bit 6
	(Vendetta) MD drive strength
	    0 =	 8 mA
	    1 = 12 mA
 6	NA# assertion control for PCI slave accesses when asynchronous PCI
	  clock is used
	0 no pipelining for accesses to PCI slave
	1 pipelining enabled for accesses to PCI slave for an asynchronous PCI
	  implementation; this bit is overridden if bit 7 is set
 5	(Viper) enable support for Intel standard BSRAM
	    0 no support for Intel standard BSRAM
	    1 support for Intel standard BSRAM; should be set only if using two
	      banks of synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM.
	(Vendetta) reserved
 4	(Viper only) enable fast BRDY# generation for PCI cycles
 3	(Viper only) enable fast FRAME# generation for PCI cycles	    
 2	(Viper only) byte merging/piping control
	0 no pipelining when byte merging is on
	1 pipelining enabled along with byte merging
 1	pipelined synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. support; this bit is applicable only if
	  register 11h bit 3 is set
	0 standard synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. installed (Viper only)
	1 pipelined synchronous SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. installed
 0	Cyrix linear burst mode support
	0 normal Intel standard burst mode
	1 support for Cyrix linear burst mode
SeeAlso: #P0189,#P0214,#P0219


Bitfields for OPTi "Viper"/"Vendetta" Tristate Control register:
Bit(s)	Description	(Table P0217)
  7	(Viper) reserved; must be written to 0
	(Vendetta) ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. retry (1)
 6	(Viper) reserved; must be written to 0
	(Vendetta) RAS line drive strength
	    0 = 16 mA
	    1 =	 4 mA
 5	(Viper) voltage selection for the CASsee Communicating Applications Specification# lines 7-0
	    0 CASsee Communicating Applications Specification# lines 7-0 are driven out at 5.0V logic level
	    1 CASsee Communicating Applications Specification# lines 7-0 are driven out at 3.3V logic level
	(Vendetta) CAS1# and CAS5# drive strength
	    0 =	 8 mA
	    1 = 16 mA
 4	(Viper) programmable current drive for the MA[X], RAS[X]# and the DWE#
	  lines
	(Vendetta) memory address lines and write enable line drive strength
	0 driving capability on these lines is 4mA
	1 driving capability on these lines is 16mA
 3	enable tristate CPU(Central Processing Unit) The microprocessor which executes programs on your computer. interface during Suspend and during CPU(Central Processing Unit) The microprocessor which executes programs on your computer. power-off
 2	enable tristate PCI interface during Suspend and during PCI power-off
 1	enable tristate cache interface during Suspend and cache power-off
 0	enable the pull-up/pull-down resistors during Suspend and power-off
SeeAlso: #P0189,#P0219


Bitfields for OPTi "Viper" (82C557) Memory Decode Control register 3:
Bit(s)	Description	(Table P0218)
 7	DIRTYWE# RAS5# selection; if six DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. banks are chosen, then the line
	  will become RAS#5, if this bit is set
	0 DIRTYWE# functions as DIRTYWE# (six banks of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. are not chosen)
	1 DIRTYWE# functions as RAS#5 (six banks of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. are chosen)
	(Vendetta must be set to RAS5# function (1))
 6-4	(Viper) full decode for logical bank 5 (RAS#5) if register 13h bit 7
	  and register 19h bit 7 are set (see #P0212)
	(Vendetta) full decode for logical bank 5 (RAS5#) if register 13h
	  bit 7 set (see #P0212)
 3	MA11/RAS#4 selection; if five DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. banks are chosen, then the MA11 line
	  will become RAS#4, if this bit is set
	0 MA11 functions as MA11 (the fifth bank of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. is not chosen)
	1 MA11 functions as RAS#4 (five banks of DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. have been chosen)
	(Vendetta must be set to RAS4# function (1))
 2-0	(Viper) full decode for logical bank 4 (RAS#4) if register 13h bit 7
	  and register 19h bit 3 are set (see #P0212)
	(Vendetta) full decode for logical bank 4 (RAS4#) if register 13h
	  bit 7 set (see #P0212)
Notes:	(Viper) if bit 7 is set, then a combined Dirty/Tag SRAM(Static Random Access Memory)  RAM which typically consists of one flip-flop per bit of memory.  Unlike DRAMs, static RAM retains its contents as long as power is applied.  Because there is no need to refresh the contents of memory addresses which are read, SRAM is faster than DRAM, but it is more expensive and typically is available in much smaller sizes than DRAM because each bit occupies more space on the chip.  See also DRAM. solution must
	   be implemented or else it will not have a Dirty RAM(Random Access Memory)	See also DRAM, SRAM.
	(Viper) if bit 3 is set, then none of the DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. banks will support the
	  8M*36 or 16M*36 options
SeeAlso: #P0189,#P0219
                                                                                


PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - OPTi "Vendetta" (82C750) CHIPSET - SYSTEM CONTROL REGISTERS
Note:	every access to PORTIBM PC Portable (uses same BIOS as XT) 0024h must be preceded by a write to PORTIBM PC Portable (uses same BIOS as XT) 0022h,
	  even if the same register is being accessed a second time
SeeAlso: PORTIBM PC Portable (uses same BIOS as XT) 0022h"82C206"

0022  ?W  index for accesses to data port (see #P0219)
0023  RW  DMAsee Direct Memory Access clock select (see #P0087)
0024  RW  chip set data


(Table P0219)
Values for OPTi "Vendetta" (82C750) system control registers:
 00h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. control register 1 (see #P0220)
 01h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. control register 2 (see #P0192)
 02h	cache control register 1 (see #P0193)
 03h	cache control 2 (see #P0194)
 04h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 1 (see #P0195)
 05h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 2 (see #P0197)
 06h	shadow RAM(Random Access Memory)	See also DRAM, SRAM. control register 3 (see #P0198)
 07h	tag test register (see #P0199)
 08h	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. cache control register (see #P0200)
 09h	system memory function register (see #P0201)
 0Ah	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. hole A address decode register 1 (see #P0202)
 0Bh	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. hole B address decode register 2 (see #P0203)
 0Ch	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. hole higher address (see #P0204)
 0Dh	clock control register (see #P0205)
 0Eh	PCI master burst control register 1 (see #P0206)
 0Fh	PCI master burst control register 2 (see #P0207)
 10h	miscellaneous control register 1 (see #P0208)
 11h	miscellaneous control register 2 (see #P0209)
 12h	miscellaneous control register 3 (see #P0221)
 13h	memory decode control register 1 (see #P0211)
 14h	memory decode control register 2 (see #P0213)
 15h	PCI cycle control register 1 (see #P0214)
 16h	dirty/tag RAM(Random Access Memory)	See also DRAM, SRAM. control register (see #P0215)
 17h	PCI cycle control register 2 (see #P0216)
 18h	tristate control register (see #P0217)
 19h	memory decode control register 3 (see #P0218)
 1Ah	memory shadow control register 1 (see #P0222)
 1Bh	memory shadow control register 2 (see #P0223)
 1Ch	EDO SDRAM control register (see #P0224)
 1Dh	miscellaneous control register 4 (see #P0225)
 1Eh	BOFF# control register (see #P0226)
 1Fh	EDO timing control register (see #P0227)
 20h	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. burst control register (see #P0228)
 21h	PCI concurrence control register (see #P0229)
 22h	inquire cycle control register (see #P0230)
 23h	pre-snoop control register (see #P0231)
 24h	asymmetric DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register (see #P0232)
 25h	GUI memory location register (see #P0233)
 26h	UMA control register (see #P0234)
 27h	self refresh timing register (see #P0235)
 28h	SDRAM burst and latency control register (see #P0236)
 29h	SDRAM selection register (see #P0237)
 2Ah	PCI-to-DRAM deep buffer size register (see #P0238)
 2Bh	EDO/SDRAM time-out register (see #P0239)
 2Ch	CPU-to-DRAM buffer control register (see #P0240)
 2Dh	bank-wise EDO timing selection register (see #P0241)
 2Eh	PCI master - GUI retry control register (see #P0242)
 2Fh	CASsee Communicating Applications Specification address setup time control register (see #P0243)
 30h-7Fh reserved
 80h	PIC 1 ICW1 read-back register (read-only)
 81h	PIC 1 ICW2 read-back register (read-only)
 82h	PIC 1 ICW3 read-back register (read-only)
 83h	PIC 1 ICW4 read-back register (read-only)
 84h	reserved
 85h	PIC 1 OCW2 read-back register (read-only)
 86h	PIC 1 OCW3 read-back register (read-only)
 87h	reserved
 88h	PIC 2 ICW1 read-back register (read-only)
 89h	PIC 2 ICW2 read-back register (read-only)
 8Ah	PIC 2 ICW3 read-back register (read-only)
 8Bh	PIC 2 ICW4 read-back register (read-only)
 8Ch	reserved
 8Dh	PIC 2 OCW2 read-back register (read-only)
 8Eh	PIC 2 OCW3 read-back register (read-only)
 8Fh	refresh address register (see #P0244)
 90h	CTSC0LB (PIT counter 0 low byte) read-back register (read-only)
 91h	CTSC0HB (PIT counter 0 high byte) read-back register (read-only)
 92h	CTSC1LB (PIT counter 1 low byte) read-back register (read-only)
 93h	CTSC1HB (PIT counter 1 high byte) read-back register (read-only)
 94h	CTSC2LB (PIT counter 2 low byte) read-back register (read-only)
 95h	CTSC2HB (PIT counter 2 high byte) read-back register (read-only)
 96h	byte pointer register (read-only)
	(byte 2 pointer value)
 97h-ACh reserved
 ADh	general purpose chip select control register (see #P0270)
 AEh-DFh reserved
 E0h	GREEN mode control/enable status (see #P0245)
 E1h	EPMI control/GREEN event timer (see #P0246)
 E2h	GREEN event timer initial count register (see #P0247)
 E3h	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. event enable register 1 (see #P0248)
 E4h	IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. event enable register 2 (see #P0249)
 E5h	DREQ event enable register (see #P0250)
 E6h	device cycle monitor enable register (see #P0251)
 E7h	wake-up source/programmable IO/memory address mask register (see #P0252)
 E8h	programmable I/O/MEM address range register (see #P0253)
 E9h	programmable I/O/MEM address range register (see #P0254)
 EAh	enter GREEN state port register (see #P0255)
 EBh	return to NORMAL state configuration port register (see #P0256)
 ECh	shadow register for external power control latch register (see #P0257)
 EDh	device cycle detection enable/status register (see #P0258)
 EEh	STPCLK# modulation register (see #P0259)
 EFh	miscellaneous register (see #P0260)
 F0h	device timer CLK select/enable status register (see #P0261)
 F1h	device timer 0 initial count register
 F2h	device timer 1 initial count register
 F3h	device timer IO/MEM select, mask bits register (see #P0262)
 F4h	device 0 IO/MEM address register (see #P0263)
 F5h	device 0 IO/MEM address register (see #P0264)
 F6h	device 1 IO/MEM address register (see #P0265)
 F7h	device 1 IO/MEM address register (see #P0266)
 FAh-FBh reserved
 FCh	power management control register 1 (see #P0267)
 FDh	power management control register 2 (see #P0268)
 FEh	power management control register 3 (see #P0269)
 FFh	general purpose chip select control register (see #P0270)


Bitfields for OPTi "Vendetta" DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. control register 1:
Bit(s)	Description	(Table P0220)
 7	reserved
 6	SDRAM pipeline fix (1)
 5-0	reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" miscellaneous control register 3:
Bit(s)	Description	(Table P0221)
 7	buffered DMAsee Direct Memory Access register 8Fh latch to bits 23-16 of SA lines disable
 6-0	reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" memory shadow control register 1:
Bit(s)	Description	(Table P0222)
 7	reserved
 6-5	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. bus utilization time guarantee
	00 = no guarantee
	01 = 1 of every 15 microseconds
	10 = 2 of every 15 microseconds
	11 = 4 of every 15 microseconds
 4	C8000-DFFFF shadow granularity
	0 = 16 KB
	1 =  8 KB
 3-2	CE000-CFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM.; applicable if bit 4 is set (see #P0196)
 1-0	CA000-CBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM.; applicable if bit 4 is set (see #P0196)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" memory shadow control register 2:
Bit(s)	Description	(Table P0223)
 7-6	DE000-DFFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM.; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 5-4	DA000-DBFFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM.; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 3-2	D6000-D7FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM.; applicable if register 1Ah bit 4 is set
	  (see #P0196)
 1-0	D2000-D3FFF read/write control; determines the R/W control for these
	  segments of the shadow RAM(Random Access Memory)	See also DRAM, SRAM.; applicable if register 1Ah bit 4 is set
	  (see #P0196)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" EDO SDRAM control register:
Bit(s)	Description	(Table P0224)
 7-2	bank 5-0 EDO SDRAM usage
	0 = standard page mode DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
	1 = EDO SDRAM
 1	reserved
 0	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. access CASsee Communicating Applications Specification pulse width
	0 = determined by register 01h bit 3
	1 = 1 CPUCLK
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" miscellaneous control register 4:
Bit(s)	Description	(Table P0225)
 7-6	reserved
 5	DWE# timing
	0 = normal
	1 = removed 1 CLK earlier
 4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read leadoff cycle
	0 = normal
	1 = 1 CLK reduced
 3	system memory DMAsee Direct Memory Access access disable
 2	reserved
 1	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. mode B0000-BFFFF access
	0 = main memory
	1 = PCI bus
 0	SMM(System Management Mode) A special CPU mode typically invoked on changes in power-supply status.  In this mode, additional hidden memory becomes available for storing the CPU's state and a control program to deal with the needs of power management or other critical events. mode A0000-AFFFF access
	0 = main memory
	1 = PCI bus
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" BOFF# control register:
Bit(s)	Description	(Table P0226)
 7	PCI master read cycle
	0 = wait IRDY# assert before TRDY# assert
	1 = generate TRDY# when checking IRDY# status
 6	reserved (1)
 5	reserved
 4	A0000-BFFFF PCI retry cycle BOFF# generation
	0 = not generated if bit 3 set
	1 = generated if bit 3 set
 3	deadlock situation avert
	0 = no avert
	1 = assert BOFF#
 2	reserved (1)
 1-0	reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" EDO timing control register:
Bit(s)	Description	(Table P0227)
 7	0 = normal
	1 = EDO detection conflict generation (bit 6 set)
 6	0 = normal fast page mode
	1 = detect EDO
 5	NA# generation
	0 = aggresive
	1 = normal
 4	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read cycle lead-off 1 CLK reduce enable
 3-2	reserved
 1	hidden refresh block AHOLD disable
 0	D0000-DFFFF cacheable in L1 and L2
	0 = not cacheable
	1 = cacheable; area has to be read/writable and shadowed
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. burst control register:
Bit(s)	Description	(Table P0228)
 7	reserved (1)
 6	PCI master access HITM# cycle DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. write post enable
 5	reserved
 4	PCI master parity enable
 3-2	PCI master cycle DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. write burst cycle
	00 = reserved
	01 = X-3-3-3
	10 = X-2-2-2
	11 = X-1-1-1
 1-0	PCI master cycle DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read burst cycle
	00 = reserved
	01 = X-3-3-3
	10 = X-2-2-2
	11 = X-1-1-1
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" PCI concurrence control register:
Bit(s)	Description	(Table P0229)
 7	concurrence timer
	0 = conservative
	1 = aggressive
 6-5	PCI master and CPU(Central Processing Unit) The microprocessor which executes programs on your computer./L2 concurrence
	00 = no concurrence
	x1 = PCI write invalid cycles
	1x = PCI read multiple and read line cycles
 4-3	reserved
 2	0 = if tag = 11011111b => invalid combination
	1 = if cache = 256K, tag = 00001100b => invalid combination (CF0000h).
	    if cache > 256K, tag = 10111111b => invalid combination
	  (valid only when bit 1 set)
 1-0	reserved (1)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" inquire cycle control register:
Bit(s)	Description	(Table P0230)
 7	reserved
 6-5	new mode pre-snoop function
	00 = disable
	11 = enable
 4	HRQ synchronous to LCLK enable (must be 1 for ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. retry)
 3-1	reserved
 0	write hit cycle lead-off time when combining Dirty/Tag RAM(Random Access Memory)	See also DRAM, SRAM.
	0 = single write hit lead-off cycle = 5 cycles
	1 = single write hit lead-off cycle = 4 cycles
Note:	bit 0 should be set same as register 16h bit 4
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" pre-snoop control register:
Bit(s)	Description	(Table P0231)
 7	reserved
 6	0 = bank 0 selected as first bank
	1 = bank 0 selected as last bank
 5	PCI X-1-1-1 write invalidate pre-snoop enable
 4	PCI X-1-1-1 read multiple and read line pre-snoop enable
 3	fast NA cache hit half clock shift enable
 2-1	reserved (1)
 0	reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" asymmetric DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. configuration register:
Bit(s)	Description	(Table P0232)
 7-6	logical bank 3 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
	00 = symmetric
	01 = asymmetric x8
	10 = asymmetric x9
	11 = asymmetric x10
 5-4	logical bank 2 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
 3-2	logical bank 1 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
 1-0	logical bank 0 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. type
Note:	banks 4 and 5 do not support asymmetric DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM.
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" GUI memory location register:
Bit(s)	Description	(Table P0233)
 7-3	GUI memory location bits 31-27
 2	UMA size
	0 = decided by register 26h bits 5-4
	1 = 0.5MB (register 26h bits 5-4 = 00)
 1-0	reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" UMA control register:
Bit(s)	Description	(Table P0234)
 7	ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. master to DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. cycle CASsee Communicating Applications Specification width
	0 = controlled by ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. read/write command pulse width
	1 = 2 LCLKs
 6	ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT.  See also EISA. SA address latch
	0 = pass-through
	1 = on only for retry
 5-4	GUI memory size
	00 = 1MB (0.5MB if register 25h bit 2 set)
	01 = 2MB
	10 = 3MB
	11 = 4MB
 3	66MHz 5-2-2-2 EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read timing enable
 2-1	GUI priority
	00 = normal
	01 = wait 2 CLKs for low priority GUI request
	11 = high
 0	UMA support enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" self refresh timing register:
Bit(s)	Description	(Table P0235)
 7-6	reserved
 5	PCI master write line invalid cycle HITM# or L2 dirty no stop enable
 4	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. single write hit not dirty cycle second T2 AHOLD generate enable
 3	fast NA# with L2 cache enable
 2-0	self refresh
	000 = disable, use external refresh pin
	001-011 = reserved
	100 = 66MHz external CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock
	101 = 60MHz external CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock
	110 = 50MHz external CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock
	111 = 40MHz external CPU(Central Processing Unit) The microprocessor which executes programs on your computer. clock
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" SDRAM burst and latency control register:
Bit(s)	Description	(Table P0236)
 7	CS# delay enable
 6-4	SDRAM CASsee Communicating Applications Specification# latency
	000 = reserved
	001 = 1
	010 = 2
	011 = 3
	100-111 = reserved
 3	0 = sequential write-through
	1 = interleaved write-through
 2-0	SDRAM burst length
	000 = 1
	001 = reserved
	010 = 4
	011-111 = reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" SDRAM selection register:
Bit(s)	Description	(Table P0237)
 7	pipeline read
	0 = 7-1-1-1-5-1-1-1-1
	1 = 7-1-1-1-2-1-1-1-1
 6	reserved
 5	timing
	     tRP     tRAS    tMRS
	00 = 2 CLKs  4 CLKs  3 CLKs
	01 = 4 CLKs  5 CLKs  3 CLKs
	10 = 3 CLKs  6 CLKs  2 CLKs
	11 = rsvd    7 CLKs  rsvd
	tRP: command activate precharge time
	tRAS: command precharge RAS active time
	tMRS: mode register set cycle time
 4-0	bank 4-0 SDRAM enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" PCI-to-DRAM deep buffer size register:
Bit(s)	Description	(Table P0238)
 7	reserved
 6-5	PCI master read cycle GUI request time-out
	00 = FP mode, grant DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bus when possible
	01 = SDRAM or EDO time-out
	10-11 = FP mode, SDRAM, or EDO time-out
 4	PCI-to-DRAM deep buffer PCI TRDY# wait state
	0 = 0 wait state (X-1-1-1)
	1 = 1 wait state (X-2-2-2)
 3	PCI-to-DRAM deep buffer write burst enable
 2	PCI-to-DRAM deep buffer read burst enable
 1-0	PCI-to-DRAM deep buffer size
	00 = 16 dwords
	01 = 24 dwords
	10-11 = reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" EDO/SDRAM time-out register:
Bit(s)	Description	(Table P0239)
 7-4	SDRAM time-out count on GUI request - 9 CLKs
	  (delay count +9 CLKs)
 3-0	EDO time-out count on GUI request
	  (delay count +6 CLKs)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" CPU-to-DRAM buffer control register:
Bit(s)	Description	(Table P0240)
 7	concurrent CPU-to-PCI read and CPU-to-DRAM write enable
 6	reserved
 5	cache miss dirty cycle CPU-to-DRAM buffer control
	1 = supply data to CPU(Central Processing Unit) The microprocessor which executes programs on your computer. before previous data write-back
	  (CPU-to-DRAM buffer must be enabled)
 4-3	reserved
 2	DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read cycle BOFF# assert enable
 1	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. bus ownership data merge enable
 0	write data while buffer flush enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" bank-wise EDO timing selection register:
Bit(s)	Description	(Table P0241)
 7	reserved
 6	predictive reading enable
 5-0	bank 5-0 EDO DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory.  Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents.  Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM.  See also Refresh, SRAM. read cycle
	0 = default
	1 = 5-X-X-X (66MHz)/4-X-X-X (50MHz) enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" PCI master - GUI retry control register:
Bit(s)	Description	(Table P0242)
 7-6	reserved
 5	USBsee Universal Serial Bus module enable
 4	reserved
 3	CPU-to-PCI FIFO control module enable
 2	reserved
 1	PCI master HITM# cycle, GUI high priority request before first BRDY#
	0 = retry all
	1 = retry only PCI master read
 0	GUI cycle PCI master request retry
	0 = retry all
	1 = retry reads, accept writes
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" CASsee Communicating Applications Specification address setup time control register:
Bit(s)	Description	(Table P0243)
 7	page miss cycle CASsee Communicating Applications Specification column address delay
	0 = default
	1 = 1 CLK
 6	burst mode and length
 5	reserved
 4-3	burst mode and length
	bits 6 and 4-3:
	000 = mode 0, RWM 5
	001 = mode 1, RWM 5, BLEN 2
	010 = BLEN 3
	011 = BLEN 4
	100 = mode 0, RWM 4
	101 = mode 2, RWM 4, BLEN 1
	110 = BLEN 2
	111 = BLEN 3
	RWM: refresh request water mark
	BLEN: minimum number of burst refresh cycles
	mode 0: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU(Central Processing Unit) The microprocessor which executes programs on your computer./PCI request pending, preempt refresh burst when
		count<RWM; else refresh until count=0, then refresh ahead up
		to 3/7
	mode 1: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU(Central Processing Unit) The microprocessor which executes programs on your computer./PCI request pending, preempt refresh burst when
		count<RWM and performed refresh cycles>=BLEN; else refresh
		until count=0, then refresh ahead up to 3/7
	mode 2: generate refresh request on RWM reach/cross; if high priority
		GUI request pending, preempt refresh burst at end of current
		cycle; if CPU(Central Processing Unit) The microprocessor which executes programs on your computer. request pending, preempt refresh burst when
		performed refresh cycles>=BLEN; if PCI request pending,
		preempt refresh burst when count<RWM and performed refresh
		cycles>=BLEN; else refresh until count=0, then refresh ahead
		up to 3/7
 2-0	refresh ahead
	000 = burst refresh disable
	001 = starting bank 0, no refresh ahead
	010 = starting bank 0, refresh ahead up to 3
	011 = starting bank 0, refresh ahead up to 7
	100 = burst refresh disable
	101 = starting bank dynamic, no refresh ahead
	110 = starting bank dynamic, refresh ahead up to 3
	111 = starting bank dynamic, refresh ahead up to 7
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" refresh address register:
Bit(s)	Description	(Table P0244)
 7-0	during buffered DMAsee Direct Memory Access cycle reflected on bits 23-16 of SA lines,
	  bits 15-10 of SA lines cleared
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" GREEN mode control/enable status:
Bit(s)	Description	(Table P0245)
 7	power management SMI# generation enable
 6	GREEN event SMI# generation
	(read)
	0 = GREEN event did not generate SMI#
	1 = GREEN event generated SMI#
	(write)
	0 = disable GREEN event SMI# generation
	1 = enable GREEN event SMI# generation (if bit 7 set)
 5	reload GREEN event timer/wake-up event SMI# generation
	(read)
	0 = wake-up event did not generate SMI#
	1 = wake-up event generated SMI#
	(write)
	0 = disable wake-up event SMI# generation
	1 = enable wake-up event SMI# generation (if bit 7 set)
 4	power management status (read-only)
	0 = NORMAL
	1 = GREEN
 3	power management PPWRL# generation enable
 2	GREEN event PPWRL# generation enable (if bit 3 set)
 1	reload GREEN event timer/wake-up event PPWRL# generation enable
	  (if bit 3 set)
 0	software generation of GREEN event
	0 = no action
	1 = generate GREEN event (if register E1h bit 0 set)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" EPMI control/GREEN event timer:
Bit(s)	Description	(Table P0246)
 7-6	GREEN event timer CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 5	EPMI0# polarity
	0 = EPMI0# triggered on falling edge
	1 = EPMI0# triggered on rising edge
 4	EPMI0# debounce enable
 3	EPMI0# polarity
	0 = determined by bit 5
	1 = EPMI0# triggered on transition
 2	GREEN event timer time-out GREEN event generation
	(read)
	0 = GREEN event timer time-out did not cause GREEN event
	1 = GREEN event timer time-out did cause GREEN event
	(write)
	0 = disable GREEN event timer time-out GREEN event generation
	1 = enable GREEN event timer time-out GREEN event generation
 1	EPMI0# trigger GREEN event generation
	(read)
	0 = EPMI0# trigger did not cause GREEN event
	1 = EPMI0# trigger did cause GREEN event
	(write)
	0 = disable EPMI0# trigger GREEN event generation
	1 = enable EPMI0# trigger GREEN event generation
 0	software trigger GREEN event generation
	(read)
	0 = software trigger did not cause GREEN event
	1 = software trigger did cause GREEN event
	(write)
	0 = disable software trigger GREEN event generation
	1 = enable software trigger GREEN event generation
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" GREEN event timer initial count register:
Bit(s)	Description	(Table P0247)
 7-0	time-out timer count - 2
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. event enable register 1:
Bit(s)	Description	(Table P0248)
 7-3	IRQ7-IRQ3 monitoring enable
 2	IRQ15-IRQ0 deglitch enable
 1-0	IRQ1-IRQ0 monitoring enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" IRQ(Interrupt ReQuest) A hardware line connected to the interrupt controller chip which signals that a CPU interrupt should be generated. event enable register 2:
Bit(s)	Description	(Table P0249)
 7-0	IRQ15-IRQ8 monitoring enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" DREQ event enable register:
Bit(s)	Description	(Table P0250)
 7-5	DREQ7-DREQ5 monitoring enable (if register EFh bit 6 set)
 4	reserved
 3-0	DREQ3-DREQ0 monitoring enable (if register EFh bit 6 set)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device cycle monitor enable register:
Bit(s)	Description	(Table P0251)
 7	programmable IO/MEM monitoring enable
 6	parallel ports monitoring enable
 5	video monitoring enable
 4	hard disk monitoring enable
 3	floppy disk monitoring enable
 2	keyboard monitoring enable
 1	COM1/COM3 monitoring enable
 0	COM2/COM4 monitoring enable
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" wake-up source/programmable IO/memory address:
Bit(s)	Description	(Table P0252)
 7	PREQ# monitoring enable (if register EFh bit 7 set)
 6	LDEV#/DEVSEL# monitoring enable
 5	EPMI0# trigger monitoring enable
 4	reserved
 3	programmable IO/MEM address type
	0 = I/O
	1 = non-system memory
 2-0	programmable IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 0)
	  (mask lowest n bits)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" programmable I/O/MEM address range register:
Bit(s)	Description	(Table P0253)
 7-0	I/O address bits 7-0 or non-system memory address bits 23-16
	  (use register E7h bit 3 to select I/O or non-system memory address)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" programmable I/O/MEM address range register:
Bit(s)	Description	(Table P0254)
 7-0	I/O address bits 15-8 or non-system memory address bits 31-24
	  (use register E7h bit 3 to select I/O or non-system memory address)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" enter GREEN state port register:
Bit(s)	Description	(Table P0255)
 7-0	GREEN state values for external power control latch
	  (transfered to register ECh on enter GREEN state PPWRL#)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" return to NORMAL state configuration port:
Bit(s)	Description	(Table P0256)
 7-0	NORMAL state values for external power control latch
	  (transfered to register ECh on return to NORMAL state PPWRL#)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" shadow register for external power control latch:
Bit(s)	Description	(Table P0257)
 7-0	external power control latch value
	  (write generates PPWRL#)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device cycle detection enable/status register:
Bit(s)	Description	(Table P0258)
 7	programmed range access SMI# generation
	(read)
	0 = programmed range access did not generate SMI#
	1 = programmed range access generated SMI#
	(write)
	0 = disable programmed range access SMI# generation
	1 = enable programmed range access SMI# generation
 6	LPTAbbreviation for Line PrinTer. access SMI# generation
	(read)
	0 = LPTAbbreviation for Line PrinTer. access did not generate SMI#
	1 = LPTAbbreviation for Line PrinTer. access generated SMI#
	(write)
	0 = disable LPTAbbreviation for Line PrinTer. access SMI# generation
	1 = enable LPTAbbreviation for Line PrinTer. access SMI# generation
 5	video access SMI# generation
	(read)
	0 = video access did not generate SMI#
	1 = video access generated SMI#
	(write)
	0 = disable video access SMI# generation
	1 = enable video access SMI# generation
 4	hard disk access SMI# generation
	(read)
	0 = hard disk access did not generate SMI#
	1 = hard disk access to generated SMI#
	(write)
	0 = disable hard disk access SMI# generation
	1 = enable hard disk access SMI# generation
 3	floppy disk access SMI# generation
	(read)
	0 = floppy disk access did not generate SMI#
	1 = floppy disk access generated SMI#
	(write)
	0 = disable floppy disk access SMI# generation
	1 = enable floppy disk access SMI# generation
 2	keyboard access SMI# generation
	(read)
	0 = keyboard access did not generate SMI#
	1 = keyboard access generated SMI#
	(write)
	0 = disable keyboard access SMI# generation
	1 = enable keyboard access SMI# generation
 1	COM1/COM3 access SMI# generation
	(read)
	0 = COM1/COM3 access did not generate SMI#
	1 = COM1/COM3 access generated SMI#
	(write)
	0 = disable COM1/COM3 access SMI# generation
	1 = enable COM1/COM3 access SMI# generation
 0	COM2/COM4 access SMI# generation
	(read)
	0 = COM2/COM4 access did not generate SMI#
	1 = COM2/COM4 access generated SMI#
	(write)
	0 = disable COM2/COM4 access SMI# generation
	1 = enable COM2/COM4 access SMI# generation
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" STPCLK# modulation register:
Bit(s)	Description	(Table P0259)
 7	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. STOPCLK state support enable
 6	STOPCLK state CPU(Central Processing Unit) The microprocessor which executes programs on your computer. hold enable
 5-4	reserved
 3	STPCLK# modulation enable
 2-0	STPCLK# modulation duty cycle; in effect if bit 3 set
	000 = STPCLK# = 1 always (no modulation)
	001 = STPCLK# = 1 for 1/2 period
	010 = STPCLK# = 1 for 1/4 period
	011 = STPCLK# = 1 for 1/8 period
	100 = STPCLK# = 1 for 1/16 period
	101-111 = reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" miscellaneous register:
Bit(s)	Description	(Table P0260)
 7	PREQ# wake-up enable
 6	DREQ# wake-up enable
 5	reserved
 4	GPCS1# and GPCS#2 generation for addresses in registers F4h-F7h enable
 3	reserved
 2	PPWRL# inititiate clock
	0 = 14 MHz
	1 = 33 KHz
 1	timer count read (registers E0h-E2h, EDh, F0h-F2h, FCh-FEh)
	0 = return current value
	1 = return original value
 0	reserved
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device timer CLK select/enable status register:
Bit(s)	Description	(Table P0261)
 7-6	device timer 1 CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 5-4	device timer 0 CLK period
	00 = 119 microseconds
	01 = 12.25 ms
	10 = 1.94 s
	11 = 62.5 s
 3	device timer 1 time-out GREEN event generation
	(read)
	0 = device timer 1 time-out did not cause GREEN event
	1 = device timer 1 time-out did cause GREEN event
	(write)
	0 = disable device timer 1 time-out GREEN event generation
	1 = enable device timer 1 time-out GREEN event generation
 2	device timer 0 time-out GREEN event generation
	(read)
	0 = device timer 0 time-out did not cause GREEN event
	1 = device timer 0 time-out did cause GREEN event
	(write)
	0 = disable device timer 0 time-out GREEN event generation
	1 = enable device timer 0 time-out GREEN event generation
 1	device 1 access wake-up event generation
	(read)
	0 = device 1 access did not cause wake-up event
	1 = device 1 access did cause wake-up event
	(write)
	0 = disable device 1 access wake-up event generation
	1 = enable device 1 access wake-up event generation
 0	device 0 access wake-up event generation
	(read)
	0 = device 0 access did not cause wake-up event
	1 = device 0 access did cause wake-up event
	(write)
	0 = disable device 0 access wake-up event generation
	1 = enable device 0 access wake-up event generation
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device timer IO/MEM select, mask bits register:
Bit(s)	Description	(Table P0262)
 7	device 1 address type
	0 = I/O
	1 = memory
 6-4	device 1 IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 2)
	  (mask lowest n bits)
 3	device 0 address type
	0 = I/O
	1 = memory
 2-0	device 0 IO/MEM address mask bits 2-0 (bit 3 = register FFh bit 2)
	  (mask lowest n bits)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device 0 IO/MEM address register:
Bit(s)	Description	(Table P0263)
 7-0	I/O address bits 7-0 or memory address bits 23-16
	  (use register F3h bit 3 to select I/O or memory address)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device 0 IO/MEM address register:
Bit(s)	Description	(Table P0264)
 7-0	I/O address bits 15-8 or memory address bits 31-24
	  (use register F3h bit 3 to select I/O or memory address)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device 1 IO/MEM address register:
Bit(s)	Description	(Table P0265)
 7-0	I/O address bits 7-0 or memory address bits 23-16
	  (use register F3h bit 7 to select I/O or memory address)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" device 1 IO/MEM address register:
Bit(s)	Description	(Table P0266)
 7-0	I/O address bits 15-8 or memory address bits 31-24
	  (use register F3h bit 7 to select I/O or memory address)
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" power management control register 1:
Bit(s)	Description	(Table P0267)
 7	EPMI1# GREEN event generation
	(read)
	0 = EPMI1# did not cause GREEN event
	1 = EPMI1# caused GREEN event
	(write)
	0 = disable EPMI1# GREEN event generation
	1 = enable EPMI1# GREEN event generation
 6	EPMI1# reload wake-up GREEN state timer enable
 5	EPMI1# polarity
	0 = determined by bit 4
	1 = EPMI1# triggered on transition
 4	EPMI1# polarity
	0 = EPMI1# triggered on falling edge
	1 = EPMI1# triggered on rising edge
 3	EPMI1# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" power management control register 2:
Bit(s)	Description	(Table P0268)
 7	EPMI2# GREEN event generation
	(read)
	0 = EPMI2# did not cause GREEN event
	1 = EPMI2# caused GREEN event
	(write)
	0 = disable EPMI2# GREEN event generation
	1 = enable EPMI2# GREEN event generation
 6	EPMI2# reload wake-up GREEN state timer enable
 5	EPMI2# polarity
	0 = determined by bit 4
	1 = EPMI2# triggered on transition
 4	EPMI2# polarity
	0 = EPMI2# triggered on falling edge
	1 = EPMI2# triggered on rising edge
 3	EPMI2# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" power management control register 3:
Bit(s)	Description	(Table P0269)
 7	EPMI3# GREEN event generation
	(read)
	0 = EPMI3# did not cause GREEN event
	1 = EPMI3# caused GREEN event
	(write)
	0 = disable EPMI3# GREEN event generation
	1 = enable EPMI3# GREEN event generation
 6	EPMI3# reload wake-up GREEN state timer enable
 5	EPMI3# polarity
	0 = determined by bit 4
	1 = EPMI3# triggered on transition
 4	EPMI3# polarity
	0 = EPMI3# triggered on falling edge
	1 = EPMI3# triggered on rising edge
 3	EPMI3# debounce enable
 2-0	reserved
Note:	bits 7 and 6 cannot both be set at the same time
SeeAlso: #P0219


Bitfields for OPTi "Vendetta" general purpose chip select control register:
Bit(s)	Description	(Table P0270)
 7	CPU(Central Processing Unit) The microprocessor which executes programs on your computer. type
	0 = Intel/AMD
	1 = Cyrix M1
 6	reserved
 5-4	IDE(Integrated Drive Electronics) A type of disk drive interface which essentially extends the PCIBM PC's expansion bus all the way to the drive and places the drive controller on the disk drive itself.	 See also ESDI. module device ID
	00 = C621h
	01 = D568h
	10 = D768h (ultra DMAsee Direct Memory Access)
	11 = reserved
 3	reserved
 2	GPCS2# address bit masking (fourth bit to register F3h bits 6-4)
 1	GPCS1# address bit masking (fourth bit to register F3h bits 2-0)
 0	GPCS0# address bit masking (fourth bit to register E7h bits 2-0)
Note:	indexes ADh and FFh address same register
SeeAlso: #P0219