RBIL61 - APIC BASE ADDRESS

RBIL61 - APIC BASE ADDRESS

INT 1A - PCI BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v2.0c+ - READ CONFIGURATION DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (Intel devices) {#idx35671}{#idx35868}{#idx36278}{#idx37347}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:001Bh - Pentium Pro, PentiumII - APIC BASE ADDRESS {#idx165462}{#idx165472}{#idx165474}

PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Intel 82358DT 'Mongoose' EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). CHIPSET - 82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. CONTROLLER {#idx133806}