RBIL61 - Cyrix 6x86MX

RBIL61 - Cyrix 6x86MX

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0003h - Pentium - INVALID {#idx164838}{#idx164840}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0004h - Pentium - (TR2) INSTRUCTION CACHE END BITS {#idx164857}{#idx164859}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0005h - Pentium - (TR3) CACHE DATA TEST REGISTER {#idx164874}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0010h - Pentium, Pentium Pro - TIME STAMP COUNTER REGISTER {#idx165093}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0011h - Pentium, Cyrix 6x86MX - EVENT COUNTER SELECTION AND CONTROL {#idx165105}{#idx165108}{#idx165114}{#idx165119}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0012h - Pentium, Cyrix 6x86MX - EVENT COUNTER #0 {#idx165212}{#idx165215}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0013h - Pentium, Cyrix 6x86MX - EVENT COUNTER #1 {#idx165218}{#idx165221}

Opcodes List {#idx174595}