Interrupt List - Release 61 (16jul00)
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CACHE CONTROL
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RBIL61 - CACHE CONTROL
CMOS
(Complementary Metal-Oxide-Semiconductor) A type of integrated circuit design known for its low power consumption.
2Ch -
AMI
American Megatrends, Inc.
(American Megatrends, Inc.) A hardware, software and firmware company founded in 1985.
- Second Hard Disk user defined: # of Sectors per track
{#idx169105}
{#idx169108}
INT 16 - Compaq Systempro and higher - CACHE CONTROLLER STATUS
{#idx27075}
INT 16 - Compaq Systempro and higher - DISABLE CACHE CONTROLLER
{#idx27115}
INT 16 - Compaq Systempro and higher - ENABLE CACHE CONTROLLER
{#idx27100}
INT 1A - PCI
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
v2.0c+ - FIND PCI DEVICE
{#idx32699}
INT 1A - PCI
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
v2.0c+ - READ CONFIGURATION
DWORD
Doubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address.
(Intel devices)
{#idx35603}
{#idx36005}
{#idx36175}
{#idx36373}
{#idx36401}
{#idx36430}
{#idx36434}
{#idx36523}
{#idx36547}
INT 1A - PCI
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
v2.0c+ - READ CONFIGURATION
DWORD
Doubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address.
(VIA Technologies devices)
{#idx34464}
{#idx34496}
{#idx34502}
INT 21 - SMARTDRV.SYS v3.x only - IOCTL - CACHE CONTROL
{#idx47777}
MEM 0040h:000Eh - SEGMENT OF EXTENDED
BIOS
(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly.
DATA SEGMENT
(
PS/2
IBM PS/2, any model
, newer BIOSes)
{#idx161087}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0007h - Pentium -
(TR5)
CACHE CONTROL
{#idx165144}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0119h - PentiumII -
"BBL_CR_CTL"
- CACHE CONTROL REGISTER
{#idx165850}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:011Eh - Pentium II -
"BBL_CR_CTL3"
L2 CACHE CONTROL REGISTER 3
{#idx165894}
{#idx165901}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
8000h:0007h - Pentium -
(TR5)
CACHE CONTROL
{#idx166517}
PORT
IBM PC Portable (uses same BIOS as XT)
0022-0023 - CHIP SET DATA
{#idx134287}
PORT
IBM PC Portable (uses same BIOS as XT)
0022-0023 - Intel 82358DT 'Mongoose'
EISA
(Enhanced Industry-Standard Architecture) A 32-bit superset of the
IBM
International Busiuness Machines
AT
IBM PC AT
's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus).
CHIPSET - 82359
DRAM
(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM.
CONTROLLER
{#idx133757}
PORT
IBM PC Portable (uses same BIOS as XT)
0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips
{#idx134860}
{#idx134865}
{#idx134932}
{#idx134948}
{#idx135118}
{#idx135187}
{#idx135192}
{#idx135214}
{#idx135438}
{#idx136824}
{#idx136829}
{#idx136841}
PORT
IBM PC Portable (uses same BIOS as XT)
0080 - MANUFACTURING DIAGNOSTICS
PORT
IBM PC Portable (uses same BIOS as XT)
{#idx140726}
{#idx140934}
PORT
IBM PC Portable (uses same BIOS as XT)
00A8-00A9 - Via VT82C496G
"Pluto"
- CONFIGURATION REGISTERS
{#idx141511}
{#idx141532}
{#idx141740}
{#idx141843}
PORT
IBM PC Portable (uses same BIOS as XT)
00A8-00AC - Via VT82C570M
"Apollo Master"
- CONFIGURATION REGISTERS
{#idx141907}
{#idx141926}