Interrupt List - Release 61 (16jul00)
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PentiumMMX
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RBIL61 - PentiumMMX
Bibliography
{#idx167437}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0006h - Pentium -
(TR4)
CACHE TAG
{#idx164910}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0007h - Pentium -
(TR5)
CACHE CONTROL
{#idx164926}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0008h - Pentium, PentiumMMX -
(TR6)
TLB COMMAND
{#idx164945}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0009h - Pentium, PentiumMMX -
(TR7)
TLB DATA
{#idx164958}
{#idx164970}
{#idx164972}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:000Bh - Pentium, PentiumMMX -
(TR9)
BRANCH TARGET BUFFER TAG
{#idx164991}
{#idx165001}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:000Ch - Pentium, PentiumMMX -
(TR10)
BRANCH TARGET BUFFER TARGET
{#idx165004}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:000Dh - Pentium, PentiumMMX -
(TR11)
BRANCH TARGET BUFFER CONTROL
{#idx165012}
{#idx165021}
{#idx165026}
{#idx165028}
{#idx165030}
{#idx165036}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:000Eh - Pentium, K6, C6 -
(TR12)
NEW FEATURE CONTROL
{#idx165048}
{#idx165053}
MSR
(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors.
0000h:0011h - Pentium, Cyrix 6x86MX - EVENT COUNTER SELECTION AND CONTROL
{#idx165146}
Notes
{#idx164766}