RBIL61 - read/write

CALL xxxxh:xxxxh - Plug-and-Play BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v1.0A {#idx160143}{#idx160146}{#idx160156}{#idx160159}{#idx160177}{#idx160180}{#idx160193}{#idx160196}{#idx160222}{#idx160228}{#idx160235}{#idx160452}

CMOS(Complementary Metal-Oxide-Semiconductor) A type of integrated circuit design known for its low power consumption. 0Ah - RTCsee Real-Time Clock - STATUS REGISTER A (read/write) (usu 26h) {#idx168228}

CMOS(Complementary Metal-Oxide-Semiconductor) A type of integrated circuit design known for its low power consumption. 0Bh - RTCsee Real-Time Clock - STATUS REGISTER B (read/write) {#idx168253}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 18h/00h - Raytheon TMC2361 - FILTER AND TEST PATTERN REGISTER {#idx170286}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 18h/01h - Raytheon TMC2361 - ENCODER CONTROL REGISTER {#idx170305}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 18h/02h - Raytheon TMC2361 - RESET CONTROL REGISTER {#idx170321}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 86h/20h - ITT VPX 32xx - IF compensation {#idx170500}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. 8Ah/20h - ITT VDP 3108 - IF compensation {#idx171563}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. A0h - EEPROM (Xicor X24C01A, etc.) {#idx172290}{#idx172321}

I2C(also IIC; the "2" is superscripted) Inter-Integrated Circuit Bus -- A moderate-speed serial communications bus originally invented by Philips in the early 1980s for consumer-electronics applications, such as inter-chip communication in a television set or high-end stereo. The I2C bus has recently appeared on PCs in video capture boards and similar devices, as well as (surprisingly) SDRAM DIMMs (for the on-board serial EEPROM). The ACCESS.bus is a derivative of the I2C bus which forms the physical layer of the Universal Serial Bus. Similary, the SMBus (System Management Bus) also uses I2C as its physical layer. F8h - 10-bit addressing - Device addresses 0xxh {#idx172536}

INT 10 - DOS/V - READ/WRITE DOUBLE-BYTE CHARACTER SET CHARACTERS/ATTRIBUTES {#idx3335}

INT 10 - VESA(Video Electronics Standards Association) An industry group which sets both hardware and software standards and recommendations. The term VESA is also used to denote compliance with the VESA SuperVGA BIOS Extensions, a standard set of video BIOS functions for accessing video modes of higher resolution than those defined by IBMInternational Busiuness Machines. OEM(Original Equipment Manufacturer) a company which purchases components that are resold as part of its own products under the company's own brand name, e.g. a Gateway 2000-branded monitor may actually be a Mag or NEC monitor. Extensions - API(Application Program[ming] Interface) The defined set of calls which a program may make to interact with or request services of the operating system or environment under which it is running. Because the inputs and outputs of the calls are well-defined, a program using the API can continue using the identical calls even if the internal organization of the program providing the API changes. {#idx4886}{#idx4890}

INT 10 - VIDEO - SAVE/RESTORE VIDEO STATE (PS50+IBM PS/2 Models 50,60,70,80,VGAVideo Graphics Array(Video Graphics Array) The video adapter introduced with the IBMInternational Busiuness Machines PS/2IBM PS/2, any model series of computers.) {#idx3628}

INT 13 - 2M - FORMAT TRACK {#idx8332}

INT 13 - EZ-Drive - INSTALLATION CHECK {#idx11581}

INT 13 - HARD DISK - PSIBM PS/2, any model/1 and newer PS/2IBM PS/2, any model - IDENTIFY DRIVE {#idx10070}

INT 13 - SWBIOS - INSTALLATION CHECK {#idx11530}

INT 13 - XBIOS - COMMAND {#idx11431}{#idx11455}

INT 14 - ARTICOM - SET INTERNAL SEND/RECEIVE VECTOR {#idx14267}

INT 14 - I1541 - SEND SECONDARY ADDRESS FOR LISTEN {#idx13768}

INT 15 - IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. SurePath BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. - ACCESS LOADABLE-ABIOS SIGNATURE {#idx21152}

INT 15 - Intel System Management Bus - GET DEVICE ADDRESSES {#idx19990}

INT 15 - PS/2IBM PS/2, any model Model 95 - READ/WRITE CMOS(Complementary Metal-Oxide-Semiconductor) A type of integrated circuit design known for its low power consumption. MEMORY {undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx23031}{#idx23041}

INT 16 - PCIBM PC Tools v5.1-8.0 DESKTOP - CREATE/OPEN/DELETE FILE {undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx28041}

INT 19 - SYSTEM - BOOTSTRAP LOADER {#idx30262}

INT 1A - Intel Plug-and-Play AUTO-CONFIGURATION - INSTALLATION CHECK {#idx38757}

INT 1A - PCI BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. v2.0c+ - READ CONFIGURATION DWORDDoubleword; four bytes. Commonly used to hold a 32-bit segment:offset or selector:offset address. (Intel devices) {#idx35422}{#idx35432}{#idx35511}{#idx35529}{#idx35533}{#idx37293}{#idx38526}

INT 1A - PCMCIA v2 Card Services - API(Application Program[ming] Interface) The defined set of calls which a program may make to interact with or request services of the operating system or environment under which it is running. Because the inputs and outputs of the calls are well-defined, a program using the API can continue using the identical calls even if the internal organization of the program providing the API changes. {#idx31939}

INT 21 - Brian Antoine Seagate ST-01 SCSI(Small Computer Systems Interface) A system-independent expansion bus typically used to connect hard disks, tape drives, and CD-ROMs to a computer. A host adapter connects the SCSI bus to the computer's own bus. See also ESDI, IDE..SYS - IOCTL - EXECUTE COMMANDS {#idx48480}{#idx48508}{#idx48532}

INT 21 - DOS 1+ - OPEN FILE USING FCBsee File Control Block {#idx41792}

INT 21 - DOS 2+ - "OPEN" - OPEN EXISTING FILE {#idx45114}

INT 21 - DOS 3.0+ - CREATE NEW FILE {#idx52874}

INT 21 - DOS 3.0+ - CREATE TEMPORARY FILE {#idx52842}

INT 21 - DOS 3.2+ - IOCTL - GENERIC BLOCK DEVICE REQUEST {#idx49104}{#idx49112}

INT 21 - DOS 4.x only - internal - GET DOS SWAPPABLE DATA AREAS {obsolete, undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx53501}

INT 21 - FlashTek X-32VM - ALLOCATE PROTECTED-MODE SELECTOR {protected mode} {#idx44644}

INT 21 - Network Driver Interface Specification (NDIS(Network Driver Interface Specification) A hardware-independent network interface developed by Microsoft and 3com. See also Packet Driver, TCP/IP.) 2.0.1 - PROTOCOL MANAGER {#idx46999}

INT 21 - Novell NetWare - DATA MIGRATION SUPPORT MODULE INFORMATION {#idx70048}

INT 21 - PCIBM PC/TCP(Transmission Control Protocol) A higher level (session layer) of the TCP/IP protocol suite. See also IP, TCP/IP. IPCUST.SYS - READ CONFIGURATION DATA {#idx45264}

INT 21 - PCIBM PC/TCP(Transmission Control Protocol) A higher level (session layer) of the TCP/IP protocol suite. See also IP, TCP/IP. IPCUST.SYS - RESET CONFIGURATION DATA READ POINTER {#idx47989}

INT 21 - PCIBM PC/TCP(Transmission Control Protocol) A higher level (session layer) of the TCP/IP protocol suite. See also IP, TCP/IP. IPCUST.SYS - WRITE CONFIGURATION DATA {#idx45583}

INT 21 - Phar Lap 386/DOS-Extender - GET PAGE TYPES {protected mode, partially documented} {#idx43015}

INT 21 - Phar Lap 386/DOS-Extender v3.0+ - READ/WRITE SYSTEM REGISTERS {protected mode} {#idx43210}

INT 21 - Phar Lap 386/DOS-Extender v4.0+ - READ/WRITE IDTsee Interrupt Descriptor Table DESCRIPTOR {protected mode} {#idx43318}

INT 21 - Phar Lap 386/DOS-Extender VMM v3.0 - READ/WRITE LDT DESCRIPTOR {protected mode} {#idx43162}

INT 21 - PTS-DOS 6.51 & S/DOS 1.0 - DIRECT DISK READ {undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx57117}

INT 21 - Turbo Debug HARDWARE BREAKPOINTS - READ STATUS BLOCK {#idx45238}

INT 21 - Turbo Debug HARDWARE BREAKPOINTS - SEND CMD TO HARDWARE BRKPNT DRIVER {#idx45546}

INT 21 - Windows95 - FAT32 - EXTENDED ABSOLUTE DISK READ/WRITE {#idx56636}{#idx56640}{#idx56651}

INT 21 - xDISK v3.31 - CONFIGURE {undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx48359}

INT 2F - DOS 3.2+ - SET DISK INTERRUPT HANDLER {undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx78583}

INT 2F - DRIVER.SYS support - EXECUTE DEVICE DRIVER REQUEST {undocumentedInformation about a product which is not publicly available from the manufacturer, and must be determined by reverse-engineering (disassembly, trial-and-error, etc.). Undocumented information tends to change -- often dramatically -- between successive revisions of a product, since the manufacturer has no obligation to maintain compatibility in behavior which is not explicitly stated.} {#idx75581}

INT 2F - Novell NetWare - Adv NetWare 4.0 DOS Requester - GET VLM CALL ADDRESS {#idx86983}

INT 31 - CauseWay - "AliasSel" - CREATE READ/WRITE DATA ALIAS SELECTOR {protected mode} {#idx97930}

INT 31 - CauseWay - "ExecOverlay" - LOAD AND OPTIONALLY EXECUTE APP CODE {protected mode} {#idx98309}

INT 31 - CauseWay - "GetSel" - ALLOCATE NEW SELECTOR {protected mode} {#idx97905}

INT 31 - DPMIsee DOS Protected-Mode Interface 0.9+ - SET DEBUG WATCHPOINT {protected mode} {#idx97615}

INT 31 - DPMIsee DOS Protected-Mode Interface 1.0+ - GET PAGE ATTRIBUTES {protected mode} {#idx97341}

INT 45 - Acorn BBC Master 512 - "OSFILE" - READ/WRITE FILE OR DIRECTORY INFO {#idx100593}

INT 78 - UofSalford DBOS DOS extender - API(Application Program[ming] Interface) The defined set of calls which a program may make to interact with or request services of the operating system or environment under which it is running. Because the inputs and outputs of the calls are well-defined, a program using the API can continue using the identical calls even if the internal organization of the program providing the API changes. {#idx122096}

INT 7F - Alloy MW386 v2+ - SET FCBsee File Control Block MODE {#idx125854}

INT 7F - Alloy NTNX - LOCK FILE FOR USER {#idx125781}

INT E0 - REAL/32 - "MP_MAP" - MAP PHYSICAL MEMORY {real mode} {#idx131370}

MEM C000h:xxxxh - VESA(Video Electronics Standards Association) An industry group which sets both hardware and software standards and recommendations. The term VESA is also used to denote compliance with the VESA SuperVGA BIOS Extensions, a standard set of video BIOS functions for accessing video modes of higher resolution than those defined by IBMInternational Busiuness Machines. VBE(VESA BIOS Extensions) The common software interface for video cards providing support for high resolution and bit depth. v3.0 PROTECTED MODE INFORMATION BLOCK {#idx163995}{#idx164001}{#idx164007}{#idx164013}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0002h - Pentium - (TR1) PARITY REVERSAL TEST REGISTER {#idx165053}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0004h - Pentium - (TR2) INSTRUCTION CACHE END BITS {#idx165074}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0005h - Pentium - (TR3) CACHE DATA TEST REGISTER {#idx165093}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0006h - Pentium - (TR4) CACHE TAG {#idx165126}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0008h - Pentium, PentiumMMX - (TR6) TLB COMMAND {#idx165173}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0009h - Pentium, PentiumMMX - (TR7) TLB DATA {#idx165185}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:000Bh - Pentium, PentiumMMX - (TR9) BRANCH TARGET BUFFER TAG {#idx165218}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:000Ch - Pentium, PentiumMMX - (TR10) BRANCH TARGET BUFFER TARGET {#idx165231}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0010h - Pentium, Pentium Pro - TIME STAMP COUNTER REGISTER {#idx165325}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0011h - Pentium, Cyrix 6x86MX - EVENT COUNTER SELECTION AND CONTROL {#idx165334}{#idx165372}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0012h - Pentium, Cyrix 6x86MX - EVENT COUNTER #0 {#idx165441}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0013h - Pentium, Cyrix 6x86MX - EVENT COUNTER #1 {#idx165447}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:002Ah - Pentium Pro/II - "EBL_CR_POWERON" {#idx165487}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0082h - AMD Am5k86 (AMD-K5) - ARRAY ACCESS REGISTER {#idx165578}{#idx165598}{#idx165606}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:008Bh - Pentium Pro - "BIOS_SIGN" BIOS(Basic Input/Output System) A set of standardized calls giving low-level access to the hardware. The BIOS is the lowest software layer above the actual hardware and serves to insulate programs (and operating systems) which use it from the details of accessing the hardware directly. UPDATE SIGNATURE {#idx165679}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0118h - PentiumII - "BBL_CR_DECC" READ/WRITE L2 CACHE ECC BITS {#idx165841}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0186h - Pentium Pro - "EVNTSEL0" - PERFORM. COUNTER EVENT SELECTION 0 {#idx166006}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:0187h - Pentium Pro - "EVNTSEL1" - PERFORM. COUNTER EVENT SELECTION 1 {#idx166085}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 0000h:1000h - IBMInternational Busiuness MachinesInternational Busiuness Machines) A hardware, software and other service technology company founded in 1911. 386/486 SLC - PROCESSOR OPERATION REGISTER {#idx166372}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0004h - Pentium - (TR2) INSTRUCTION CACHE END BITS {#idx166503}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0005h - Pentium - (TR3) CACHE DATA TEST REGISTER {#idx166509}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0006h - Pentium - (TR4) CACHE TAG {#idx166513}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0008h - Pentium - (TR6) TLB COMMAND {#idx166523}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0009h - Pentium - (TR7) TLB DATA {#idx166527}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:000Bh - Pentium - (TR9) BRANCH TARGET BUFFER TAG {#idx166536}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:000Ch - Pentium - (TR10) BRANCH TARGET BUFFER TARGET {#idx166540}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0010h - Pentium - TIME STAMP COUNTER {#idx166554}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0011h - Pentium - EVENT COUNTER SELECTION AND CONTROL {#idx166559}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0012h - Pentium - EVENT COUNTER #0 {#idx166563}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:0013h - Pentium - EVENT COUNTER #1 {#idx166567}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:001Bh - Pentium - FLOATING POINT - LAST EXCEPTION OPCODE {#idx166592}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:001Dh - Pentium - PROBE MODE CONTROL REGISTER {#idx166599}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:001Eh - Pentium - ??? {#idx166614}

MSR(Model-Specific Register) Additional, indirectly-accessible, registers containing control or status information about various aspects of the processor such as caches, performance counters, and the like. These registers, accessible via the RDMSR and WRMSR instructions, were added with the Pentium and later-model 486 processors. 8000h:001Fh - Pentium - ??? {#idx166617}

Notes {#idx168166}{#idx168200}

Opcodes List {#idx174311}{#idx174314}{#idx174323}{#idx174732}{#idx174765}{#idx174831}{#idx174874}{#idx174938}{#idx175017}{#idx175113}{#idx175268}{#idx175652}{#idx175733}{#idx175883}

PORTIBM PC Portable (uses same BIOS as XT) 0022-0023 - Intel 82358DT 'Mongoose' EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). CHIPSET - 82359 DRAM(Dynamic Random Access Memory) RAM memory which essentially consists of a tiny capacitor for each bit of memory. Since capacitors do not hold a charge indefinitely, DRAM must be constantly refreshed to avoid losing its contents. Also, the process of reading the contents of the memory are destructive, meaning extra time must be spent restoring the contents of memory addresses which are accessed, so DRAM is slower than SRAM. See also Refresh, SRAM. CONTROLLER {#idx133915}{#idx133936}

PORTIBM PC Portable (uses same BIOS as XT) 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips {#idx134889}{#idx134891}{#idx134893}{#idx135255}{#idx135618}{#idx135625}{#idx135632}{#idx135966}{#idx136039}{#idx136257}{#idx136260}{#idx136266}{#idx136273}{#idx136284}{#idx136287}{#idx136290}{#idx136293}{#idx136308}{#idx136311}{#idx137023}{#idx137026}{#idx137034}{#idx137037}{#idx137040}{#idx137043}{#idx137146}

PORTIBM PC Portable (uses same BIOS as XT) 0024-0029 - HEADLAND HTK340 SHASTA 386/486 CHIPSET {#idx138928}

PORTIBM PC Portable (uses same BIOS as XT) 0028-002A - 80486 "Deep Green" motherboard - ??? {#idx139058}

PORTIBM PC Portable (uses same BIOS as XT) 0040-005F - PIT - PROGRAMMABLE INTERVAL TIMER (8253, 8254) {#idx139250}

PORTIBM PC Portable (uses same BIOS as XT) 0044-0047 - Microchannel - PROGRAMMABLE INTERVAL TIMER 2 {#idx139290}

PORTIBM PC Portable (uses same BIOS as XT) 0080 - MANUFACTURING DIAGNOSTICS PORTIBM PC Portable (uses same BIOS as XT) {#idx140661}{#idx140678}

PORTIBM PC Portable (uses same BIOS as XT) 00A8-00A9 - Via VT82C496G "Pluto" - CONFIGURATION REGISTERS {#idx141652}

PORTIBM PC Portable (uses same BIOS as XT) 01F0-01F7 - HDC 1 (1st Fixed Disk Controller) (ISA(Industry-Standard Architecture) The expansion bus used by the IBMInternational Busiuness Machines PCIBM PC/ATIBM PC AT. See also EISA., EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus).) {#idx143195}{#idx143205}{#idx143296}

PORTIBM PC Portable (uses same BIOS as XT) 0330-0333 - Adaptec 154xB/154xC SCSI(Small Computer Systems Interface) A system-independent expansion bus typically used to connect hard disks, tape drives, and CD-ROMs to a computer. A host adapter connects the SCSI bus to the computer's own bus. See also ESDI, IDE. adapter (default address) {#idx145966}{#idx145999}{#idx146004}

PORTIBM PC Portable (uses same BIOS as XT) 0340-035F - Adaptec AHA-152x SCSI(Small Computer Systems Interface) A system-independent expansion bus typically used to connect hard disks, tape drives, and CD-ROMs to a computer. A host adapter connects the SCSI bus to the computer's own bus. See also ESDI, IDE. adapter {#idx146531}

PORTIBM PC Portable (uses same BIOS as XT) 0360-036F - PCIBM PC network (ATIBM PC AT) {#idx146880}

PORTIBM PC Portable (uses same BIOS as XT) 03B0-03BF - MDA(Monochrome Display Adapter) A text-only video adapter introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also CGAColor Graphics Adapter, HGC. (Monochrome Display Adapter based on 6845) {#idx147892}{#idx147986}{#idx147999}

PORTIBM PC Portable (uses same BIOS as XT) 03D4-03D5 - COLOR VIDEO - CRT CONTROL REGISTERS {#idx149916}

PORTIBM PC Portable (uses same BIOS as XT) 03D6-03D7 - CGAColor Graphics Adapter(Color/Graphics Adapter) One of the two video display boards introduced together with the original IBMInternational Busiuness Machines PCIBM PC. See also HGC, MDA. (Color Graphics Adapter) - MIRRORS OF 03D4/03D5 {#idx150288}

PORTIBM PC Portable (uses same BIOS as XT) 03F0-03F7 - FDC 1 (1st Floppy Disk Controller) second FDC at 0370 {#idx151489}

PORTIBM PC Portable (uses same BIOS as XT) 0AD6-0AD7 - Chips & Technologies PCIBM PC Video (82C9001A) - CONTROL REGISTERS {#idx153418}

PORTIBM PC Portable (uses same BIOS as XT) 1C00-1CBF - Adaptec AIC-777x EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). SCSI(Small Computer Systems Interface) A system-independent expansion bus typically used to connect hard disks, tape drives, and CD-ROMs to a computer. A host adapter connects the SCSI bus to the computer's own bus. See also ESDI, IDE. controller in EISA(Enhanced Industry-Standard Architecture) A 32-bit superset of the IBMInternational Busiuness Machines ATIBM PC AT's expansion bus (which is now known as the ISA or Industry-Standard Architecture bus). slot 1 {#idx154281}{#idx154284}

PORTIBM PC Portable (uses same BIOS as XT) xxxx - Ensoniq AudioPCI ES1370 - CONTROL REGISTERS {#idx158681}{#idx158805}{#idx158813}{#idx158853}

PORTIBM PC Portable (uses same BIOS as XT) xxxx - Future Domain TMC-3260 PCI SCSI(Small Computer Systems Interface) A system-independent expansion bus typically used to connect hard disks, tape drives, and CD-ROMs to a computer. A host adapter connects the SCSI bus to the computer's own bus. See also ESDI, IDE. adapter {#idx158073}{#idx158076}{#idx158153}{#idx158882}